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公开(公告)号：US10924120B1
公开(公告)日：2021-02-16
申请号：US16696285
申请日：2019-11-26
发明人： Deepesh John , Samiul Haque Khan , Vibhor Mittal , Shravan Lakshman , Teja Singh
摘要： An oscillator circuit includes a phase-locked loop (PLL) with a plurality of voltage controlled oscillator (VCO), a clock divider circuit receiving the VCO phase outputs and outputting a first stage clock signal with an adjustable clock period related to the PLL period based on selecting a combination of two of the VCO phase outputs. The first stage clock signal has a balanced duty cycle at frequencies that are related to the PLL frequency by even fractional divisions of the VCO phase output period based on the quantity VCO phase outputs, and an unbalanced duty cycle at frequencies that are related by odd fractional divisions. A duty cycle adjustment (DCA) circuit receives the first stage clock signal selectively adjusts a falling edge of the first stage clock signal to provide an even duty cycle and feeds a resulting signal to the second stage clock signal output.
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公开(公告)号：US10768225B1
公开(公告)日：2020-09-08
申请号：US16296614
申请日：2019-03-08
发明人： Venkat Krishnan Ravikumar , Wen Tsann Lua , Gopinath Ranganathan , Yi Xuan Seah , Shei Lay Phoa , Nathan Linarto , Jiann Min Chin
IPC分类号： G01R31/311
摘要： A control system for placing an optic probe includes a receiver circuit that receives reflected light produced from the optic probe and provides a laser probe (LP) waveform of the reflected light in response to an activation of a trigger signal. A combinational logic analysis (CLA) processor provides a CLA waveform in response to simulating an optical response at a target location on a surface of a cell of a device under test to a test pattern. A test controller receives the CLA waveform and the LP waveform, and has a first output for providing the trigger signal, a second output for providing the test pattern, and a third output for providing a position signal. The test controller updates the position signal to move the optic probe closer to the target location according to a degree of fit between the LP waveform and the CLA waveform.
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公开(公告)号：US10734977B1
公开(公告)日：2020-08-04
申请号：US16379874
申请日：2019-04-10
发明人： Wenhuan Yu , Abdulkerim L. Coban
摘要： In one form, an analog-to-digital converter (ADC) includes first and second ring-oscillator ADCs, a modulus subtractor, and a decimation filter. The first and second ring-oscillator ADCs are responsive to true and complement input voltages, respectively, have outputs for providing first and second digital phase signals, respectively, each having a first predetermined number of bits sampled at a first frequency. The modulus subtractor subtracts the second digital phase signal from the first digital phase signal to provide a phase difference signal. The decimation filter differentiates the phase difference signal at a second frequency lower than said the frequency to provide a frequency signal proportional to a differential voltage between the true input voltage and the complementary input voltage, and decimates the frequency signal to provide a digital code having a second predetermined number of bits greater than the first predetermined number of bits.
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公开(公告)号：US10673204B2
公开(公告)日：2020-06-02
申请号：US15451905
申请日：2017-03-07
摘要： A laser driver is described which comprises a resonant circuit having an inductor and a DC blocking capacitor. A biasing voltage reference is operably coupled to the inductor. A controller is operable for controlling the resonant circuit for selectively connecting the inductor between high and low impedance. The DC blocking capacitor is operable for connecting to a laser diode.
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公开(公告)号：US10509752B2
公开(公告)日：2019-12-17
申请号：US15964647
申请日：2018-04-27
IPC分类号： G11C5/06 , G06F13/38 , G06F13/42 , H01L25/065 , G06F13/40
摘要： A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.
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公开(公告)号：US10416293B2
公开(公告)日：2019-09-17
申请号：US15376464
申请日：2016-12-12
摘要： A histogramming readout circuit is described. The readout circuit comprises a time to digital converter (TDC) configured to continually report time-stamps defining an arrival time of a laser clock and a signal output from a photosensor. Memory is provided for 10 storing TDC events. A programmable processor is configured to implement a state machine. The state machine being operable to save a time-stamp when a TDC event is detected; determine the time of flight of each of the photons detected by the photosensor; use each calculated time of flight to address a memory location; build up a histogram of the TDC data values using the memory locations as time-bins; and maintain a pointer to a maximum memory location where the highest number of TDC event resides. A calculator is operable to read the value of the maximum memory location and one or more adjacent time-bins either side for processing.
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公开(公告)号：US10389337B2
公开(公告)日：2019-08-20
申请号：US15584729
申请日：2017-05-02
发明人： Hua Zhu , Kaiwei Yao
摘要： A ramp generator includes a current generator, a current mirror, and a first capacitor. The current generator has an input for receiving a clock signal, and an output for providing a current proportional to a frequency of the clock signal using a first transistor having first and second current electrodes and a control electrode, an amplifier that establishes a reference voltage on the second current electrode of the first transistor, and a variable resistor coupled between the second current electrode of the second transistor and ground whose resistance is set according to the frequency of the clock signal. The current mirror has an input coupled to the first terminal of the first transistor, and a second terminal. The first capacitor has a first terminal coupled to the output of the current mirror and providing a ramp signal, and a second terminal coupled to the first power supply voltage terminal.
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公开(公告)号：US10345445B2
公开(公告)日：2019-07-09
申请号：US15212537
申请日：2016-07-18
发明人： Marek Hustava , Tomas Pikula , Tomas Suchy
摘要： In one form, an acoustic signal is generated for an acoustic transducer, where the acoustic transducer is susceptible to reverberation that defines a close proximity indication zone. The start of a close proximity indication zone window is defined after the generation of the acoustic signal at a first time. During the close proximity indication zone window, a signal is received from the acoustic transducer. When the signal is received, an obstacle is detected in the close proximity indication zone if the magnitude of a first pulse received from the transducer at a second time is less than a first threshold but greater than a second threshold for a debounce time. Additionally, a magnitude of a second pulse received from the transducer outside the close proximity indication zone window at a third time should be less than the second threshold but greater than a third threshold for the debounce time. In this form, the third time is equal to the first time plus two times the difference between the second time and the first time.
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公开(公告)号：US10312799B1
公开(公告)日：2019-06-04
申请号：US15974392
申请日：2018-05-08
发明人： Joel Turchi , Radim Mlcousek , Lukas Olivik
摘要： In one form, a power factor correction (PFC) controller, comprising includes a regulation circuit, a dead-time detection circuit, and a pulse width modulator. The regulation circuit provides a control voltage in response to a feedback voltage received at a feedback input terminal, wherein the feedback voltage is proportional to an output voltage. The dead-time detection circuit has an input coupled to a zero current detection input terminal, and an output for providing a dead-time signal. The pulse width modulator is responsive to the control voltage and the dead-time signal to provide a drive signal that controls conduction of a switch to improve a power factor of an offline converter, wherein the pulse width modulator modulates both an on-time and a switching period of the drive signal using the dead-time signal in a discontinuous conduction mode.
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公开(公告)号：US10276610B2
公开(公告)日：2019-04-30
申请号：US15582158
申请日：2017-04-28
IPC分类号： H01L27/14 , H01L27/144 , H01L31/02 , H01L31/107 , H01L31/024 , H01L25/16 , H01L23/00 , H01L23/48
摘要： The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line.
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