公开(公告)号：US20030043654A1

公开(公告)日：2003-03-06

申请号：US10234076

申请日：2002-09-03

发明人： Johann Pfeiffer ,  Bernd Klehn ,  Helmut Fischer

IPC分类号： G11C007/00

CPC分类号： G11C11/4097 ,  G11C11/4076 ,  G11C2207/229

摘要： A method for accessing memory cells of a cell field of a DRAM module organized in rows and columns, in which an addressed row is addressed over a word line, and a desired column is addressed over a bit line pair, is described. For a write access, a stored charge is transferred to all bit line pairs, a column address is detected by a column decoder, the appertaining word line is activated, and a read amplifier amplifies the potential on the addressed bit lines. The write access is initiated simultaneously with an activation of the word line.

摘要翻译： 描述了一种用于访问以行和列组织的DRAM模块的单元字段的存储单元的方法，其中寻址行通过字线寻址，并且通过位线对寻址所需的列。 对于写访问，存储的电荷被传送到所有位线对，列地址由列解码器检测，相关字线被激活，读取放大器放大寻址位线上的电位。 写入访问与字线的激活同时启动。

公开(公告)号：US06515892B1

公开(公告)日：2003-02-04

申请号：US09959906

申请日：2001-11-13

申请人： Kiyoo Itoh ,  Kazuo Nakazato

发明人： Kiyoo Itoh ,  Kazuo Nakazato

IPC分类号： G11C1124

CPC分类号： G11C11/405 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.

摘要翻译： 一种半导体集成电路器件，其利用包含晶体管来写入信息的存储单元和存储MOSFET来保持栅极中的信息电压，放置为与写入数据线和读取数据线相交的字线，用于连接到控制器 写入晶体管的端子和用于响应于来自所述写入晶体管的选择信号而从所述存储单元发出对应于读取信号的所述读取数据线上的输出的存储单元阵列，并且借助于数据选择电路，从 所述多条读取数据线从数据线选择电路连接到第一或第二公共数据线，在第一周期内将所述读取数据线预充电到第一电压，借助于 所述存储器单元的第二存储MOSFET设置为在所述第二周期内选择的所述字线的状态，将所述第一和第二公共数据线预充电到第三伏特 在所述第一周期内的所述第一和所述第二电压之间，并且在所述第二周期内通过使用所述另一个上的预充电电压来放大在所述第二周期内由所述数据线选择电路选择的读数据线上出现在任一公共数据线上的读信号 公共数据线作为参考电压。

公开(公告)号：US06496444B2

公开(公告)日：2002-12-17

申请号：US09919327

申请日：2001-07-31

申请人： Frankie F. Roohparvar

发明人： Frankie F. Roohparvar

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4243 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/18 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/105 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2216/22

摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.

摘要翻译： 同步闪速存储器包括非易失性存储器单元阵列。 存储器件具有与SDRAM兼容的封装配置。 在一个实施例中，同步存储器件包括以行和列排列的存储单元阵列。 提供时钟连接以接收外部提供的时钟信号。 存储器在第一和第二外部提供的有效命令之间的时间段期间不需要预充电时间段。

公开(公告)号：US06484246B2

公开(公告)日：2002-11-19

申请号：US09383193

申请日：1999-08-26

申请人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

发明人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G06F1202

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： A dynamic random access memory device includes a bit line, a memory cell coupled to the bit line, and a word line coupled to the memory cell. A read activation time between receiving a read command for a read operation in order to read data: from the memory cell and activating the word-line-may be different from a write activation time between receiving a write command for a write operation in order to write data to the memory cell and activating the word line.

摘要翻译： 动态随机存取存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。 为了从存储器单元读取数据和激活字线，读取操作的读取命令之间的读取激活时间可能不同于接收写入操作的写入命令之间的写入激活时间，以便于 将数据写入存储单元并激活字线。

公开(公告)号：US06462584B1

公开(公告)日：2002-10-08

申请号：US09503108

申请日：2000-02-11

申请人： Robert J. Proebsting

发明人： Robert J. Proebsting

IPC分类号： H03F1900

CPC分类号： G11C7/065 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4091 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

摘要： A current tail circuit and method for a differential transistor pair affords the capability of sensing an input differential signal having a low common mode voltage when using, for example, an NMOS differential transistor pair. A current source device and a capacitor may be employed to provide at the common node of the differential transistor pair what appears to be a constant current source connected to a “negative voltage.” In one embodiment particularly useful when using an NMOS differential pair, one terminal of a capacitor is precharged to VDD and the other terminal is precharged to VSS (i.e., ground). When the amplifier needs to sense its differential input signal, a control signal turns off precharge transistors and couples the capacitor terminal previously precharged to VSS to the common-source node of a differential transistor pair. The capacitor terminal previously precharged to VDD is driven toward VSS, preferably with a controlled current source, which couples the common-source node of the differential pair from VSS toward a voltage below VSS. As soon as the common-source node voltage is low enough for at least one side of the differential pair to conduct a current substantially equal to the controlled current source, the common-source node voltage is substantially clamped at that voltage. The actual voltage resulting on the common-source node depends on the transistor characteristics, the particular voltages present on the gates of the differential pair, and the magnitude of the controlled current source. For some operating conditions, this voltage may be above ground rather than below ground, but the “tail” current of the differential pair nonetheless remains equal to the magnitude of current through the device driving the other terminal of the capacitor from VDD toward VSS.

公开(公告)号：US20020051378A1

公开(公告)日：2002-05-02

申请号：US09917777

申请日：2001-07-31

发明人： Takashi Ohsawa

IPC分类号： G11C011/24

CPC分类号： H01L29/7841 ,  G11C7/02 ,  G11C7/18 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229 ,  G11C2211/4016 ,  H01L21/84 ,  H01L21/845 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/785

摘要： An 1 bit memory cell MC is composed of one MOS transistor having a floating bulk region which is electrically isolated from others. A gate electrode 13 of the MOS transistor is connected to a word line WL, a drain diffusion region 14 thereof is connected to a bit line BL, and a source diffusion region 15 thereof is connected to a fixed potential line SL. The memory cell stores a first threshold state in which majority carriers produced by impact ionization are injected and held in the bulk region 12 of the MOS transistor and a second threshold state in which the majority carriers in the bulk region 12 of the MOS transistor are emitted by a forward bias at a pn junction on the drain side as binary data. Thereby, a semiconductor memory device in which a simple transistor structure is used as a memory cell, enabling dynamic storage of binary data by a small number of signal lines can be provided.

摘要翻译： 1位存储单元MC由具有与其他电气隔离的浮动块区的一个MOS晶体管组成。 MOS晶体管的栅电极13连接到字线WL，其漏极扩散区域14连接到位线BL，其源极扩散区域15连接到固定电位线SL。 存储器单元存储第一阈值状态，其中通过冲击电离产生的多数载流子被注入并保持在MOS晶体管的体区域12中，并且第二阈值状态在MOS晶体管的体区12中的多数载流子被发射 通过在漏极侧的pn结处的正向偏压作为二进制数据。 因此，可以提供一种半导体存储器件，其中使用简单的晶体管结构作为存储单元，能够通过少量信号线实现二进制数据的动态存储。

公开(公告)号：US20020046331A1

公开(公告)日：2002-04-18

申请号：US10014457

申请日：2001-12-11

发明人： Paul G. Davis ,  Frederick A. Ware ,  Craig E. Hampel

IPC分类号： G06F012/00

CPC分类号： G11C7/1039 ,  G06F13/1626 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2218 ,  G11C2207/229

摘要： A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.

摘要翻译： 描述了一种用于将数据存储在存储器件中的方法和装置。 该装置被配置为执行以下步骤。 该方法采用两步技术，允许无序完成读写操作。 当写入操作需要完成读取操作所需的资源时，被写入的数据被存储在存储器件中的写入数据缓冲器中。 写入数据被存储在缓冲器中，直到数据路径可用于将数据传送到存储器件的存储器核心。 一旦资源空闲（或存储设备或其控制器强制写入完成），数据将使用现在免费的数据路径写入存储器设备的存储器内核。

公开(公告)号：US06356485B1

公开(公告)日：2002-03-12

申请号：US09503048

申请日：2000-02-12

申请人： Robert J. Proebsting

发明人： Robert J. Proebsting

IPC分类号： G11C1604

CPC分类号： G11C11/40618 ,  G11C7/065 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

摘要： A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. An exemplary 18 MBit memory array integrated circuit includes four banks of arrays and a write queue for storing at least one pending write cycle. At least a portion of the address information associated with a pending internal write operation is compared to corresponding address information associated with a subsequently-received write cycle request to determine whether a first group of memory cells to be otherwise written by the pending internal write operation and a second group of memory cells to be otherwise written by another internal write operation corresponding to a subsequently-received write cycle request may instead be both written using a single internal write operation. If so, then the pending internal write operation is skipped, the write data associated with the subsequently-received write cycle request is merged into, and supersedes any commonly-addressed data bits of, the write data associated with the pending internal write operation, and a single internal write operation is performed to write the merged data. Alternatively, if the first and second groups of memory cells cannot be written using a single internal write operation, the pending internal write operation is performed in its normal order, and then another internal write operation is performed to write data associated with the subsequently-received write cycle request.

摘要翻译： 多个实施例中公开了高性能动态存储器阵列结构以及相关支持电路的各种实施例。 示例性的18MBit存储器阵列集成电路包括四组阵列和用于存储至少一个未决写入周期的写入队列。 将与待处理的内部写入操作相关联的地址信息的至少一部分与与随后接收到的写入周期请求相关联的对应地址信息进行比较，以确定要由待处理的内部写入操作另外写入的第一组存储器单元，以及 另一方面，通过与随后接收到的写周期请求相对应的另一内部写入操作来写入的第二组存储器单元可以替代地使用单个内部写操作来写入。 如果是这样，则跳过待决的内部写入操作，与随后接收到的写入周期请求相关联的写入数据被合并到并替代与待处理的内部写入操作相关联的写入数据的任何共同寻址的数据位，以及 执行单个内部写入操作来写入合并的数据。 或者，如果第一组和第二组存储器单元不能使用单个内部写入操作来写入，则以其正常顺序执行未完成的内部写入操作，然后执行另一个内部写入操作以写入与随后接收的数据相关联的数据 写周期请求。

公开(公告)号：US06212109B1

公开(公告)日：2001-04-03

申请号：US09372320

申请日：1999-08-11

申请人： Robert J. Proebsting

发明人： Robert J. Proebsting

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C7/04 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/104 ,  G11C2207/229 ,  H01L27/10891 ,  H01L27/10897

摘要： A high performance dynamic memory array architecture is disclosed in several embodiments, along with various embodiments of associated supporting circuitry. In an exemplary embodiment during an internal write operation, write circuitry supplies a small differential voltage to the selected bit line sense amplifiers, which “swallows” the normal read signal, before bit line sensing. The bit line sense amplifiers then “write” the level into the memory cell during normal latching. This provides for internal write operations which proceed, for many embodiments, at the same speed as internal read operations by letting a selected bit line sense amplifier restore the voltage levels onto the selected bit lines in accordance with the data to be written, rather than in accordance with the data previously stored in a selected memory cell. A write cycle may be designed to take the same very short time as a read cycle, rather than the longer time typically required to first sense old data, then modify it with the data to be written. The address and data for a write cycle are preferably queued to eliminate dead cycles on the data bus, and the actual write operation to physically store the write data into the selected memory cells postponed at least until the next external write cycle is received.

摘要翻译： 多个实施例中公开了高性能动态存储器阵列结构以及相关支持电路的各种实施例。 在内部写入操作中的示例性实施例中，写入电路在位线感测之前向所选择的位线读出放大器提供小的差分电压，其被“吞下”正常读取信号。 位线检测放大器然后在正常锁存期间将电平“写入”到存储单元中。 这提供了对于许多实施例，以与内部读取操作相同的速度进行的内部写入操作，通过使所选择的位线读出放大器根据要写入的数据将电压电平恢复到所选位线上，而不是在 根据先前存储在所选择的存储单元中的数据。 写周期可以被设计为与读周期相同的非常短的时间，而不是首先感测旧数据通常需要较长的时间，然后用要写入的数据进行修改。 用于写周期的地址和数据优选地被排队以消除数据总线上的死循环，并且实际写入操作以物理地将写入数据存储到所选择的存储器单元中，至少延迟到接收到下一个外部写周期。

公开(公告)号：US06185256B2

公开(公告)日：2001-02-06

申请号：US09062586

申请日：1998-04-20

申请人： Miyoshi Saito ,  Junji Ogawa

发明人： Miyoshi Saito ,  Junji Ogawa

IPC分类号： H04B330

CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

摘要： A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.

摘要翻译： 信号传输系统被构造为通过消除由前面的数据引入的符号间干扰成分，通过信号传输线路传输数据，而不需要为每一位预充电信号传输线。 信号传输线具有以分支结构或层次结构组织的多个可切换信号传输线，从多个信号传输线中的每一个连接至少一个读取数据的目标单元，以及读出电路，包括： 用于消除符号间干扰分量的电路连接到信号传输线，其中，符号间干扰成分消除电路减少了在多个信号传输线之间切换信号传输线时引入的噪声，从而提供平滑的符号间干扰成分消除操作 当信号传输线路被切换时。 这使连续读出成为可能，并实现了信号传输系统的整体速度的提高。