公开(公告)号：US20020067182A1

公开(公告)日：2002-06-06

申请号：US09873395

申请日：2001-06-05

Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA

Inventor： Osamu Hashimoto

IPC: G01R031/26

CPC classification number: G01R31/31922 ,  G01R31/2879 ,  G01R31/31858

Abstract: The peak of the current dissipated by semiconductor devices is dispersed and suppressed to a level below the current supply capability of a burn-in apparatus. As a result, there is obtained a semiconductor manufacturing-and-inspection apparatus which enables easy performance of a burn-in test without involvement of anomalies arising in the burn-in apparatus or limitations on the number of semiconductor devices mounted on the burn-in board. A semiconductor manufacturing-and-inspection system, which tests semiconductor devices provided in a plurality of areas on a burn-in board through use of a burn-in apparatus, includes a driver for supplying a drive signal to the semiconductor devices provided in the plurality of areas, a delay circuit which is provided for one of a plurality of drive signals output from the signal generation apparatus and delays the drive signal relative to the other drive signal; and a driver for controlling the delaying operation of the delay apparatus.

Abstract translation: 由半导体器件耗散的电流的峰值被分散和抑制到低于老化装置的电流供应能力的水平。 结果获得了半导体制造和检查装置，其能够容易地执行老化测试，而不会引起老化装置中出现的异常或者安装在老化中的半导体器件的数量的限制 板。 一种半导体制造和检查系统，其通过使用老化装置来测试在老化板上的多个区域中提供的半导体器件，包括用于向设置在多个器件中的半导体器件提供驱动信号的驱动器 为从信号发生装置输出的多个驱动信号中的一个驱动信号提供的延迟电路相对于另一个驱动信号延迟驱动信号的延迟电路; 以及用于控制延迟装置的延迟操作的驱动器。

公开(公告)号：US06352868B1

公开(公告)日：2002-03-05

申请号：US09524421

申请日：2000-03-11

Applicant: Wen-Kun Yang

Inventor： Wen-Kun Yang

IPC: G01R3126

CPC classification number: G01R31/2879

Abstract: A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal probing pads are also provided to receive voltages for stressing a gate oxide or capacitor oxide layer. A burn-in test system has a plurality of programmable power suppliers and programmable relays for providing control and power signals to a membrane or micro spring probe card used for the wafer level burn-in of multiple dice at the same time. Wafers are loaded and aligned in a prober with an automatic probing station and a hot chuck for the burn-in. The wafer level burn-in reduces the burn-in time of an integrated circuit chip from several days to several minutes.

Abstract translation: 晶圆级老化的内置电路。 老化电路包括主老化控制电路，字线控制电路和位线控制电路。 还提供多个内部探测焊盘以接收用于施加栅极氧化物或电容器氧化物层的电压。 老化测试系统具有多个可编程电源供应商和可编程继电器，用于同时向用于多个骰子的晶片级老化的膜或微型弹簧探针卡提供控制和功率信号。 晶圆被装载并在探测器中与自动探测站和用于老化的热卡盘对准。 晶圆级老化将集成电路芯片的老化时间从几天减少到几分钟。

公开(公告)号：US06351134B2

公开(公告)日：2002-02-26

申请号：US09307394

申请日：1999-05-07

Applicant: James Marc Leas ,  Robert William Koss ,  Jody John Van Horn ,  George Frederick Walker ,  Charles Hampton Perry ,  David Lewis Gardell ,  Steve Leo Dingle ,  Ronald Prilik

Inventor： James Marc Leas ,  Robert William Koss ,  Jody John Van Horn ,  George Frederick Walker ,  Charles Hampton Perry ,  David Lewis Gardell ,  Steve Leo Dingle ,  Ronald Prilik

IPC: G01R3128

CPC classification number: G01R1/07385 ,  G01R1/07314 ,  G01R31/2863 ,  G01R31/2879 ,  G01R31/2886 ,  G01R31/2889

Abstract: An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

Abstract translation: 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的电压调节器提供电源和产品芯片上的电源接口之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置将电流限制在任何产品芯片上。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。

公开(公告)号：US06349396B2

公开(公告)日：2002-02-19

申请号：US09745834

申请日：2000-12-21

Applicant: Salman Akram

Inventor： Salman Akram

IPC: G01R3128

CPC classification number: G01R31/2868 ,  G01R31/2862 ,  G01R31/2879 ,  G01R31/3025

Abstract: A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication. A method for testing an integrated circuit having operational circuitry formed thereon, optically and via radio frequency.

Abstract translation: 一种用于评估被测电路的老化测试系统，所述系统包括具有多个插座的老化板，其中至少其中之一的尺寸适于接收被测电路，测试接口电路由板支持并耦合 所述测试接口电路包括发射机和接收机; 由板支撑的电源导体，耦合到插座并且被配置为连接到电源，以在老化测试，控制和数据信号导体期间对被测电路供电，具有选择性地接收烧伤的隔室的老化炉 并且被配置为在隔间内施加热量，以及由老化炉支撑的询问器单元，所述询问器单元被配置为向测试接口电路发送命令以光学地或通过无线电通信来锻炼被测电路，并且 通过光学或通过无线电通信来接收对命令的响应。 一种在光学上和经由无线电频率测试其上形成有操作电路的集成电路的方法。

公开(公告)号：US06181146B2

公开(公告)日：2001-01-30

申请号：US08791665

申请日：1997-01-30

Applicant: Toshio Koyama

Inventor： Toshio Koyama

IPC: G01R1512

CPC classification number: G01R31/2863 ,  G01R31/2879

Abstract: A burn-in board Vcc circuit changeover socket 204A and a GND circuit changeover socket 205A wich are arranged in a wiring area between terminals 1 to 7 of an IC socket 202 and resistors 203 corresponding to these terminals. A Vcc circuit changeover socket 204B and a GND circuit changeover socket 205B are arranged in a wiring area between terminals 8 to 14 of the IC socket 202 and resistors 203 corresponding to these terminals. A Vcc circuit changeover unit 206 is fitted, for example, in the Vcc circuit changeover socket 204A and a GND circuit changeover unit 207 is fitted, for example, in the GND circuit changeover socket 205B. A first electric potential (Vcc) is supplied to the terminals 5 and 7 of the IC socket 202, and a second electric potential (GND) is supplied to the terminals 12 and 14 of the IC socket 202. The Vcc circuit changeover unit 206 and the GND circuit changeover unit 207 may have different plug-in terminals according to kinds of ICs which may be made.

Abstract translation: 在IC插座202的端子1〜7和与这些端子对应的电阻203之间的配线区域配置有老化板Vcc电路切换插座204A和GND电路切换插座205A。 在IC插座202的端子8〜14与与这些端子对应的电阻203之间的配线区域配置有Vcc电路转换插座204B和GND电路转换插座205B。 Vcc电路切换单元206例如配置在Vcc电路切换插座204A中，GND电路切换单元207例如配合在GND电路切换插座205B中。 第一电位（Vcc）被提供给IC插座202的端子5和7，并且第二电位（GND）被提供给IC插座202的端子12和14.Vcc电路切换单元206和 GND电路切换单元207可以根据可以制造的IC的种类而具有不同的插入式端子。

公开(公告)号：US6140829A

公开(公告)日：2000-10-31

申请号：US256635

申请日：1999-02-24

Applicant: Michael J. Sharpes ,  Robert L. Totorica

Inventor： Michael J. Sharpes ,  Robert L. Totorica

IPC: G01R31/28 ,  G01R31/00

CPC classification number: G01R31/2879

Abstract: A compact and modularly designed apparatus for testing and burning-in semiconductor devices comprises first and second power supplies and the use of direct current (DC) to DC converters. The first power supply provides a high voltage low amperage power source to drive the devices under test (DUTs), and the second power supply supplies 15 volts and 5 volts to drive the circuitry on the testing equipment. The high voltage and low amperage is supplied to slot boards, and the DC to DC converters alter the voltage and current to digital levels. Supplying high voltage and low amperage power through the system to a location electrically near the DUTs, then converting it with DC to DC converters to power the DUTs, allows for much smaller connectors and for a modularly designed burn-in oven.

公开(公告)号：US5966021A

公开(公告)日：1999-10-12

申请号：US627079

申请日：1996-04-03

Applicant: Victor M. Eliashberg ,  Kombupalayam M. Prakash

Inventor： Victor M. Eliashberg ,  Kombupalayam M. Prakash

IPC: G01R31/02 ,  G01R31/28 ,  G11C7/00 ,  G11C29/00

CPC classification number: G01R31/2863 ,  G01R31/2879

Abstract: An apparatus for testing an integrated circuit in an oven during burn-in. A burn-in board in the oven is electrically connected to a plurality of integrated circuit ("IC") components. A driver/interface board outside the oven is electrically connected to the burn-in board through a plurality of contacts and sends and receives a plurality of signals between the IC components and a test controller. A switch module on the burn-in board comprises a plurality of high-temperature switches for transferring signals between the plurality of IC components and the driver/interface board during burn-in. A plurality of signals entering the switch module from the driver/interface board does not exceed in number the plurality of contacts, and is fewer in number than a plurality of signals exiting the switch module to the plurality of IC components.

公开(公告)号：US5952821A

公开(公告)日：1999-09-14

申请号：US924035

申请日：1997-08-29

Applicant: Garry Gillette

Inventor： Garry Gillette

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/319 ,  G01R19/00

CPC classification number: G01R31/3004 ,  G01R31/2879 ,  G01R31/31924 ,  G01R31/2841

Abstract: A load circuit for an integrated circuit tester provides an adjustable load at a terminal of an integrated circuit device under test (DUT) when the DUT is generating an output signal at the terminal. The load circuit includes positive and negative current sources for producing positive and negative currents of magnitudes that are non-linear functions input reference voltages. A diode quad connects the negative current source to the DUT terminal when the DUT output signal is below an input threshold voltage and connects the positive current source to the DUT terminal when the DUT output signal is above the threshold voltage. The current sources provide a non-linear, exponential, transfer function between input reference voltage and output current magnitude so that the current sources provide a relatively wide output current range in response to a relatively narrow input reference voltage range.

Abstract translation: 当DUT在端子上产生输出信号时，用于集成电路测试器的负载电路提供被测集成电路器件（DUT）的端子处的可调节负载。 负载电路包括正和负电流源，用于产生非线性函数输入参考电压的正电流和负电流。 当DUT输出信号低于输入阈值电压时，二极管四极管将负电流源连接到DUT端子，当DUT输出信号高于阈值电压时，将正电流源连接到DUT端子。 电流源提供输入参考电压和输出电流幅度之间的非线性，指数传递函数，使得电流源响应于相对窄的输入参考电压范围提供相对较宽的输出电流范围。

公开(公告)号：US5391984A

公开(公告)日：1995-02-21

申请号：US786504

申请日：1991-11-01

Applicant: James L. Worley

Inventor： James L. Worley

IPC: G01R31/28

CPC classification number: G01R31/2879

Abstract: A relatively large number of test fixtures are provided for an available tester. The tester is programmed to access the individual test fixtures independently, and does so only when the devices connected to them are to be tested. When the test fixtures are not in such a test mode, local power sources provided for each fixture are used to apply stress voltages to the devices being tested. This frees the tester from the requirement for providing stressing voltages to the devices, allowing it to be efficiently used to perform testing on a larger number of devices concurrently.

Abstract translation: 为可用的测试仪提供了相对较多的测试夹具。 测试器被编程为独立访问各个测试夹具，只有当连接到它们的设备进行测试时才会这样做。 当测试夹具不处于这种测试模式时，为每个夹具提供的局部电源用于向被测设备施加应力电压。 这样可以使测试仪免受对器件施加压力的要求，从而可以有效地使用它来同时对较大数量的器件进行测试。

公开(公告)号：US4851764A

公开(公告)日：1989-07-25

申请号：US48694

申请日：1987-05-12

Applicant: Toshio Usui

Inventor： Toshio Usui

IPC: H01L21/00 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC classification number: G01R31/2863 ,  G01R31/2621 ,  G01R31/2822 ,  G01R31/2879

Abstract: An improved holding device for holding a semiconductor device, particularly a microwave semiconductor device, in a high temperature environmental testing apparatus. The holding device includes a heat block having a heat source therein, and a cooling block for cooling the microstrip matching circuits and coaxial connectors. Both blocks are spatially isolated from each other by an air space. The semiconductor device is set on the top surface of the heat block. As a result, the semiconductor device is effectively heated up to the predetermined testing temperature, while the microstrip matching circuits and the connectors are protected from the temperature rise caused by the heat flow from the heat block. Appropriate grounding arrangements for the semiconductor device are provided by a metal foil for projections on the side walls of the cooling block.