公开(公告)号：US20230180452A1

公开(公告)日：2023-06-08

申请号：US17956102

申请日：2022-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Taegyu KANG ,  Keunnam KIM ,  Sung-Min PARK ,  Taehyun AN ,  Sanghyun LEE ,  Eunsuk JANG ,  Moonyoung JEONG ,  Euichul JEONG ,  Hyungeun CHOI

IPC: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/108 ,  G11C5/04 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes a word line extended parallel to a top surface of a semiconductor substrate, a channel pattern crossing the word line and having a long axis parallel to the top surface, a bit line extended perpendicular to the top surface and in contact with a first side surface of the channel pattern, and a data storage element in contact with a second side surface of the channel pattern opposite to the first side surface. The channel pattern includes a first dopant region adjacent to the bit line, a second dopant region adjacent to the data storage element, and a channel region between the first and second dopant regions and overlapped with the word line. At least one of the first and second dopant regions includes a low concentration region adjacent to the channel region, and a high concentration region spaced apart from the channel region.

公开(公告)号：US20230112907A1

公开(公告)日：2023-04-13

申请号：US17861479

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Sub KIM ,  Junhyeok AHN ,  Myeong-Dong LEE ,  Hui-Jung KIM ,  Kiseok LEE ,  Jihun LEE ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device and a method of fabricating a semiconductor memory device, the device including a first impurity region in a substrate; a first bit line that crosses over the substrate and is connected to the first impurity region; a bit-line contact between the first bit line and the first impurity region; and a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer.

公开(公告)号：US20220336464A1

公开(公告)日：2022-10-20

申请号：US17530818

申请日：2021-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyeok AHN ,  Kiseok LEE ,  Huijung KIM

IPC: H01L27/108

Abstract: A semiconductor device includes: a substrate including a cell area and an interface area; a gate electrode disposed in the substrate within the cell area and extending in a first direction; a plurality of bit lines intersecting the gate electrode and extending in a second direction intersecting the first direction, wherein the plurality of bit lines includes a plurality of first bit lines and a plurality of second bit lines alternately disposed in the first direction; edge spacers disposed within the interface area and contacting the plurality of second bit lines; and edge insulating layers disposed between the edge spacers and contacting the plurality of first bit lines, wherein at least a portion of each of the edge insulating layers is disposed within the interface area.

公开(公告)号：US20210159231A1

公开(公告)日：2021-05-27

申请号：US16991661

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu LEE ,  Kiseok LEE ,  Woobin SONG ,  Minhee CHO

IPC: H01L27/108 ,  G11C11/4094 ,  G11C11/408

Abstract: A semiconductor memory device includes a memory cell array of a three-dimensional structure including a plurality of memory cells repeatedly arranged in a first horizontal direction and a second horizontal direction that are parallel with a main surface of a substrate and cross each other on the substrate and in a vertical direction perpendicular to the main surface, wherein each of the plurality of memory cells includes three transistors. A method of manufacturing a semiconductor memory device includes forming simultaneously a plurality of memory cells arranged in a row in a vertical direction on a substrate, wherein each of the plurality of memory cells includes three transistors.

公开(公告)号：US20210125989A1

公开(公告)日：2021-04-29

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan SHIN ,  Changkyu KIM ,  Hui-Jung KIM ,  Iljae SHIN ,  Taehyun AN ,  Kiseok LEE ,  Eunju CHO ,  Hyungeun CHOI ,  Sung-Min PARK ,  Ahram LEE ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

公开(公告)号：US20200111793A1

公开(公告)日：2020-04-09

申请号：US16707019

申请日：2019-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung KIM ,  Kiseok LEE ,  Bong-Soo KIM ,  Junsoo KIM ,  Dongsoo WOO ,  Kyupil LEE ,  HyeongSun HONG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/06

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20190287977A1

公开(公告)日：2019-09-19

申请号：US16419947

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20170180972A1

公开(公告)日：2017-06-22

申请号：US15165412

申请日：2016-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Jung KIM ,  Kiseok LEE

IPC: H04W8/00 ,  G06Q30/02 ,  H04W4/20 ,  H04W4/00 ,  H04W4/02

Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure provides a method for operating an electronic device. The method comprises transmitting a signal including a list of one or more objects, receiving a signal including beacon recognition information of at least one object included in the list of one or more objects, storing the beacon recognition information, and making a request for information on the at least one object to a server when receiving at least one beacon signal that matches with the stored beacon recognition information.

公开(公告)号：US20150365895A1

公开(公告)日：2015-12-17

申请号：US14741865

申请日：2015-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Kangjin YOON ,  Dohy HONG

IPC: H04W52/02 ,  H04W74/06

CPC classification number: H04W52/0219 ,  H04L1/00 ,  H04L1/08 ,  H04W24/00 ,  H04W52/0216 ,  H04W52/0229 ,  H04W84/12 ,  Y02D70/00 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142

Abstract: A method and an apparatus of transmitting power saving-poll (PS-Pall) for use in a wireless network are provided. The method includes a terminal in a wireless communication system determining PS-Poll transmission priorities of terminals based on identifiers of the terminals having downlink data to receive, monitoring to detect the PS-Polls of the terminals having downlink data to receive, and transmitting, when the PS-Poll of the terminal with a priority followed right by the priority of the terminal is received, the PS-Poll after expiry of an arbitrary backoff timer.

Abstract translation: 提供了一种在无线网络中使用的发送省电轮询（PS-Pall）的方法和装置。 该方法包括：无线通信系统中的终端，基于具有下行链路数据的终端的标识符确定终端的PS-Poll发送优先级，接收监视以检测具有下行链路数据接收的终端的PS调度，以及发送 接收终端优先级的终端的PS-Poll，接收终端优先级的PS-Poll，即任意退避定时器到期后的PS-Poll。