Abstract:
This invention provides a compiler, circuits and a method for generating a flash memory for integrated circuits. This invention provides a flash memory compiler which can generate flexible configurations which are a function of the flash memory array bit count. In addition, this flash compiler of this invention has the ability to optimize the resultant flash memories so as to produce the correct amount of flash array current driving capability and minimal wasting of power dissipation as a function of the flash memory array size.
Abstract:
Methods are proposed for a buck boost voltage regulator to monitor the output voltage or both the inductor current and the output voltage of the buck boost voltage regulator to control the buck boost voltage regulator to reduce the switching times of the power switches of the buck boost voltage regulator to improve the light load efficiency of the buck boost voltage regulator.
Abstract:
A pulse width modulation (PWM) Regulator System with automatically switching pulse skipping mode (PSM) is disclosed. The PWM regulator system comprises a PWM regulator, a PSM switching module and a pulse generator. The PWM regulator converts the input voltage by PWM. The PSM switching module determines to enter or exit the PSM. The pulse generator adaptively produces pulse signal for the switching regulator to operate in PSM.
Abstract:
The present invention discloses a level shift circuit which comprises: an input driver circuit; a capacitor having a first end electrically connected with the output of the input driver circuit; an output driver circuit electrically connected with a second end of the capacitor; and a feedback latch circuit electrically connected between the output of the output driver circuit and the second end of the capacitor, for maintaining the voltage level at the second end of the capacitor.
Abstract:
In a capacitor charger including a transformer having a primary winding connected with an input voltage and a secondary winding for transforming a primary current flowing through the primary winding to a secondary current flowing through the secondary winding, the primary current is adjusted according to a monitoring voltage varying with the input voltage, thereby prolonging the lifetime of the battery that provides the input voltage and improving the power efficiency of the battery.
Abstract:
The present invention discloses a charge pump down circuit which comprises three capacitors operating in three time phases. In the first time phase, the total of the voltages across the three capacitors is equal to an input voltage; in the second time phase, the voltage across the second capacitor is equal to the voltage across the third capacitor; in the third time phase, the difference between the voltages across the first and the second capacitors is equal to the voltage across the third capacitor, wherein the voltage across the third capacitor is the output voltage of the charge pump down circuit.
Abstract:
In a capacitor charger, a transformer has a primary winding connected between an input voltage and a switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding, a control apparatus and method adjusts the on-time period for the switch in response to the input voltage. The charging time and charging current are independent of the input voltage, and there is no power loss resulted from current sense to the primary current.
Abstract:
A direct current voltage boosting/bucking device includes a direct current voltage boosting circuit and a low drop-out (LDO) linear voltage converting circuit. The direct current voltage boosting circuit boosts an input voltage so as to generate an output voltage higher than the input voltage. The LDO linear voltage converting circuit converts the output voltage into a load voltage that is to be provided to a load, and controls the direct current voltage boosting circuit in accordance with a feedback signal from the load such that the output voltage and the load voltage have a minimum drop-out voltage differential therebetween and such that current flow through the load is maintained at a determined level.
Abstract:
In a capacitor charger, a transformer has a primary winding connected between an input voltage and a switch for generating a primary current flowing through the primary winding by switching the switch to thereby induce a secondary current flowing through a secondary winding of the transformer and a secondary voltage tapered from the secondary winding, a control apparatus and method adjusts the on-time period for the switch in response to the input voltage. The charging time and charging current are independent of the input voltage, and there is no power loss resulted from current sense to the primary current.
Abstract:
This invention relates to the fabrication of integrated circuit devices and more particularly to a method for reducing the otherwise excessive negative TCR of low doped polysilicon load resistors in sub-micron, NMOS based, 4 transistor SRAM cells. The problem with a high negative TCR is that cell failures can occur as operating currents drop down too close to device leakage currents, when operating at cold temperatures. The key to this invention is a novel PN junction approach which causes polysilicon resistors to become electrically thicker at colder temperatures. A vertical PN junction is formed along the entire length of a polysilicon resistor and the temperature dependent space charge region of the PN junction is used for modulating the effective electrical thickness of the resistor. Consequently, the undesirable tendency for thermally activated grain boundary conduction to decrease with cold temperatures is partially compensated by a slight concurrent increase in resistor thickness. A method is described for fabricating such novel polysilicon load resistors, which can be used for operating 4T SRAMs at temperatures, as low as −45C., while not appreciably adding to process or device complexity.