公开(公告)号：US20080010441A1

公开(公告)日：2008-01-10

申请号：US11428589

申请日：2006-07-05

申请人： Erik R. Altman ,  Vijayalakshmi Srinivasan

发明人： Erik R. Altman ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/44

CPC分类号： G06F9/44

摘要： A method for supporting and tracking a plurality of loads in an out-of-order processor being run by a program includes executing instructions on the processor, the instructions including an address from which data is to be loaded and memory locations from which load data is received, determining inputs of the instructions, determining a function unit on which to execute the instructions, storing the plurality of instructions in both a LRQ and a LIP queue, the LRQ comprising a list of the plurality of stores and the LIP comprising a list of respective addresses of the plurality of loads, dividing the LIP into a set of congruence classes, each holding a predetermined number of the loads, allowing the loads to be stored in the memory locations, snooping the load data, and allowing a plurality of snoops to selectively invalidate the load data from snooped addresses so as to maintain sequential load consistency.

摘要翻译： 一种用于支持和跟踪由程序运行的无序处理器中的多个负载的方法包括在处理器上执行指令，指令包括要从中加载数据的地址和加载数据所在的存储位置 接收，确定所述指令的输入，确定执行所述指令的功能单元，将所述多个指令存储在LRQ和LIP队列中，所述LRQ包括所述多个存储的列表，并且所述LIP包括： 多个负载的相应地址，将该LIP划分为一组一致的等级，每个等级保持预定数量的负载，允许将负载存储在存储器位置中，窥探负载数据，并允许多个监视 有选择地使来自探测地址的负载数据无效，以保持顺序的负载一致性。

公开(公告)号：US20080010440A1

公开(公告)日：2008-01-10

申请号：US11428582

申请日：2006-07-05

申请人： Erik R. Altman ,  Vijayalakshmi Srinivasan

发明人： Erik R. Altman ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/44

CPC分类号： G06F9/44

摘要： A method for supporting and tracking a plurality of stores in an out-of-order processor run by a predetermined program includes executing a plurality of instructions on the processor, each instruction including an address from which data is to be loaded and a plurality of memory locations from which load data is received, determining inputs of the instructions, determining a function unit on which to execute the instructions; storing the plurality of instructions in both a Retirement Store Queue (RSTQ) and a Forwarding Store Queue (FSTQ), the RSTQ comprising a list of the plurality of stores and the FSTQ comprising a list of respective addresses of the plurality of stores, allowing the plurality of stores to be stored in the plurality of memory locations, and allowing the plurality of stores to forward the load data only after the instructions have determined that the predetermined number of the stores has completed the series of the execution processes.

摘要翻译： 一种用于在由预定程序运行的无序处理器中支持和跟踪多个存储的方法包括在处理器上执行多个指令，每个指令包括要从其加载数据的地址和多个存储器 接收负载数据的位置，确定指令的输入，确定执行指令的功能单元; 将所述多个指令存储在退休存储队列（RSTQ）和转发存储队列（FSTQ）两者中，所述R​​STQ包括所述多个存储的列表，并且所述FSTQ包括所述多个存储的相应地址的列表， 要存储在多个存储单元中的多个存储器，并且只有在指令已经确定预定数量的存储器已经完成了一系列执行处理之后才允许多个存储器转发加载数据。

公开(公告)号：US20070043960A1

公开(公告)日：2007-02-22

申请号：US11207333

申请日：2005-08-19

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Zhigang Hu ,  Hans Jacobson ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Zhigang Hu ,  Hans Jacobson ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3867 ,  Y02D10/171 ,  Y02D10/24

摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.

摘要翻译： 用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。 资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

公开(公告)号：US20060248287A1

公开(公告)日：2006-11-02

申请号：US11118130

申请日：2005-04-29

申请人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude Rivers ,  John Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

发明人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude Rivers ,  John Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

IPC分类号： G06F13/28

CPC分类号： G06F12/0833 ,  G06F12/0897 ,  G06F2212/2542 ,  G06F2212/271

摘要： Arrangements and methods for providing cache management. Preferably, a buffer arrangement is provided that is adapted to record incoming data into a first cache memory from a second cache memory, convey a data location in the first cache memory upon a prompt for corresponding data, in the event of a hit in the first cache memory, and refer to the second cache memory in the event of a miss in the first cache memory.

摘要翻译： 提供缓存管理的安排和方法。 优选地，提供缓冲器装置，其适于将来自第二高速缓冲存储器的输入数据记录到第一高速缓冲存储器中，在第一高速缓冲存储器中的第一高速缓冲存储器 高速缓冲存储器，并且在第一高速缓冲存储器中未命中的情况下参考第二高速缓冲存储器。

公开(公告)号：US06560693B1

公开(公告)日：2003-05-06

申请号：US09459739

申请日：1999-12-10

申请人： Thomas R. Puzak ,  Allan M. Hartstein ,  Mark Charney ,  Daniel A. Prener ,  Peter H. Oden ,  Vijayalakshmi Srinivasan

发明人： Thomas R. Puzak ,  Allan M. Hartstein ,  Mark Charney ,  Daniel A. Prener ,  Peter H. Oden ,  Vijayalakshmi Srinivasan

IPC分类号： G06F1500

CPC分类号： G06F9/383 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/3836 ,  G06F9/3844

摘要： A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.

摘要翻译： 描述了使用分支指令作为预取触发器将指令和数据预取到高速缓存中的机制。 如果分支指令之后的预测执行路径与先前查看的执行路径匹配，则启动预取。 使用分支历史队列确定执行路径的这种匹配，该分支历史队列记录节目中分支的分支结果（已取/未采用）。 对于该队列中的每个分支，分支历史掩码记录下一个N个分支的结果，并且作为分支指令之后的执行路径的编码。 分支指令与掩码一起与预取地址（指令或数据地址）相关联，并且在再次执行分支时用于触发预取。 还描述了一种机制，以通过在观察到预取指令或数据的有用性之后适当地调整N的值来提高预取的及时性。