公开(公告)号：US20120299136A1

公开(公告)日：2012-11-29

申请号：US13568670

申请日：2012-08-07

Applicant: Solomon ASSEFA ,  Michael C. GAIDIS ,  Eric A. JOSEPH ,  Eugene J. O'SULLIVAN

Inventor： Solomon ASSEFA ,  Michael C. GAIDIS ,  Eric A. JOSEPH ,  Eugene J. O'SULLIVAN

IPC: H01L29/82

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

Abstract translation: 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

公开(公告)号：US20120205523A1

公开(公告)日：2012-08-16

申请号：US13455507

申请日：2012-04-25

Applicant: Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

Inventor： Solomon Assefa ,  Yurii A. Vlasov ,  Fengnian Xia

IPC: H01L31/08 ,  H03K17/06 ,  H01L23/544

CPC classification number: H01L31/107 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03529 ,  Y02E10/50

Abstract: A semiconductor photodetector may provide charge carrier avalanche multiplication at high field regions of a semiconductor material layer. A semiconductor current amplifier may provide current amplification by impact ionization near a high field region. A plurality of metal electrodes are formed on a surface of a semiconductor material layer and electrically biased to produce a non-uniform high electric field in which the high electric field strength accelerates avalanche electron-hole pair generation, which is employed as an effective avalanche multiplication photodetection mechanism or as an avalanche impact ionization current amplification mechanism.

Abstract translation: 半导体光电探测器可以在半导体材料层的高场区域提供电荷载体雪崩倍增。 半导体电流放大器可以通过在高场区域附近的冲击电离提供电流放大。 多个金属电极形成在半导体材料层的表面上并被电偏置以产生不均匀的高电场，其中高电场强度加速雪崩电子 - 空穴对产生，其被用作有效的雪崩倍增 光电检测机制或雪崩冲击电离电流放大机制。

公开(公告)号：US20120129302A1

公开(公告)日：2012-05-24

申请号：US12951597

申请日：2010-11-22

Applicant: Solomon Assefa ,  William M.J. Green ,  Yurii A. Vlasov ,  Min Yang

Inventor： Solomon Assefa ,  William M.J. Green ,  Yurii A. Vlasov ,  Min Yang

IPC: H01L21/782 ,  H01L21/762

CPC classification number: H01L21/8238 ,  G02B6/136 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/76283 ,  H01L31/02327 ,  H01L31/103 ,  H01L31/105

Abstract: Disclosed are process enhancements to fully integrate the processing of a photonics device into a CMOS manufacturing process flow. A CMOS wafer may be divided into different portions. One of the portions is for the CMOS devices and one or more other portions are for the photonics devices. The photonics devices include a ridged waveguide and a germanium photodetector. The germanium photodetector may utilize a seeded crystallization from melt process so there is more flexibility in the processing of the germanium photodetector.

Abstract translation: 公开了将光子器件的处理完全整合到CMOS制造工艺流程中的过程增强。 CMOS晶片可以被分成不同的部分。 其中一个部分用于CMOS器件，一个或多个其它部分用于光子器件。 光子器件包括脊状波导和锗光电检测器。 锗光电探测器可以利用来自熔融法的接种结晶，因此在锗光电探测器的处理中具有更大的灵活性。

公开(公告)号：US08129811B2

公开(公告)日：2012-03-06

申请号：US13088339

申请日：2011-04-16

Applicant: Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yuri A. Vlasov

Inventor： Solomon Assefa ,  Kuan-Neng Chen ,  Steven J. Koester ,  Yuri A. Vlasov

IPC: H01L33/00

CPC classification number: H01L27/0688

Abstract: Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.

Abstract translation: 提供了具有互补金属氧化物半导体（CMOS）的集成电路和用于其三维集成的光子电路和技术。 一方面，三维集成电路包括底部器件层和顶部器件层。 底部器件层包括数字CMOS电路层; 以及与数字CMOS电路层相邻的第一结合氧化物层。 顶部器件层包括衬底; 形成在与衬底相邻的绝缘体上硅（SOI）层中的模拟CMOS和光子电路层，所述SOI层具有厚度大于或等于约1微米的掩埋氧化物（BOX）; 以及与模拟CMOS和与衬底相对的光子电路层的一侧相邻的第二结合氧化物层。 底部器件层通过第一接合氧化物层和第二接合氧化物层之间的氧化物 - 氧化物键接合到顶部器件层。

公开(公告)号：US08111724B2

公开(公告)日：2012-02-07

申请号：US12498463

申请日：2009-07-07

Applicant: Solomon Assefa ,  William M. Green ,  Younghee Kim ,  Joris Van Campenhout ,  Yurii Vlasov

Inventor： Solomon Assefa ,  William M. Green ,  Younghee Kim ,  Joris Van Campenhout ,  Yurii Vlasov

IPC: H01S5/00

CPC classification number: H01L35/34 ,  G02B6/12004 ,  G02B6/1347 ,  G02B2006/12069 ,  G02F1/0147 ,  G02F1/025

Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.

Abstract translation: 电流可以通过n掺杂半导体区域，凹陷金属半导体合金部分和p掺杂半导体区域，使得掺杂半导体区域中的多数电荷载流子的扩散通过Peltier- 塞贝克效应。 此外，温度控制装置可以被配置为包括位于光电子器件附近的金属半导体合金区域，具有p型掺杂的第一半导体区域和具有n型掺杂的第二半导体区域。 因此可以控制光电子器件的温度以稳定光电器件的性能。

公开(公告)号：US07999344B2

公开(公告)日：2011-08-16

申请号：US12775084

申请日：2010-05-06

Applicant: Solomon Assefa ,  Stephen Walter Bedell ,  Yurii A. Vlasov ,  Fengnian Xia

Inventor： Solomon Assefa ,  Stephen Walter Bedell ,  Yurii A. Vlasov ,  Fengnian Xia

IPC: H01L31/00

CPC classification number: H01L31/1808 ,  G02B6/12004 ,  H01L31/02327 ,  H01L31/105 ,  H01L31/1812 ,  Y02E10/50

Abstract: An optoelectronic device comprises a photodetector feature, an interfacial layer disposed above at least a portion of the photodetector feature, and a vertical contact disposed on at least a portion of the interfacial layer. The photodetector feature comprises germanium and is operative to convert a light signal into an electrical signal. The interfacial layer comprises nickel. Finally, the vertical contact is operative to transmit the electrical signal from the photodetector feature.

Abstract translation: 光电子器件包括光电检测器特征，设置在光电检测器特征的至少一部分上方的界面层，以及设置在界面层的至少一部分上的垂直接触。 光电检测器特征包括锗并且可操作以将光信号转换成电信号。 界面层包括镍。 最后，垂直接触可操作地从光电检测器特征传输电信号。

公开(公告)号：US20110049655A1

公开(公告)日：2011-03-03

申请号：US12549799

申请日：2009-08-28

Applicant: Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

Inventor： Solomon Assefa ,  Michael C. Gaidis ,  Eric A. Joseph ,  Eugene J. O'Sullivan

IPC: H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.

Abstract translation: 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。

公开(公告)号：US20110007761A1

公开(公告)日：2011-01-13

申请号：US12498463

申请日：2009-07-07

Applicant: Solomon Assefa ,  William M. Green ,  Young-hee Kim ,  Joris Van Campenhout ,  Yurii A. Vlasov

Inventor： Solomon Assefa ,  William M. Green ,  Young-hee Kim ,  Joris Van Campenhout ,  Yurii A. Vlasov

IPC: H01S3/04 ,  G02B6/12 ,  H01L21/00

CPC classification number: H01L35/34 ,  G02B6/12004 ,  G02B6/1347 ,  G02B2006/12069 ,  G02F1/0147 ,  G02F1/025

Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.

Abstract translation: 电流可以通过n掺杂半导体区域，凹陷金属半导体合金部分和p掺杂半导体区域，使得掺杂半导体区域中的多数电荷载流子的扩散通过Peltier- 塞贝克效应。 此外，温度控制装置可以被配置为包括位于光电子器件附近的金属半导体合金区域，具有p型掺杂的第一半导体区域和具有n型掺杂的第二半导体区域。 因此可以控制光电子器件的温度以稳定光电器件的性能。

公开(公告)号：US07825000B2

公开(公告)日：2010-11-02

申请号：US11850427

申请日：2007-09-05

Applicant: Sivananda K. Kanakasabapathy ,  Solomon Assefa

Inventor： Sivananda K. Kanakasabapathy ,  Solomon Assefa

IPC: H01L21/76 ,  H01L21/00

CPC classification number: H01L43/12 ,  H01L23/544 ,  H01L27/222 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract translation: 包括磁隧道结（MTJ）装置的磁存储器件包括基片和前端线（FEOL）电路。 形成在VA ILD层的顶表面上方的通过级（VA）层间绝缘（ILD）层，底部导体层和形成在MTI器件上的MTJ器件。 包括对准标记的对准区域延伸穿过底部导体层并向下延伸到VA ILD层的顶表面下方的装置与MJT装置并置。

公开(公告)号：US07803639B2

公开(公告)日：2010-09-28

申请号：US11619623

申请日：2007-01-04

Applicant: Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

Inventor： Solomon Assefa ,  Michael C. Gaidis ,  John P. Hummel ,  Sivananda K. Kanakasabapathy

IPC: H01L21/00 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L43/12 ,  H01L21/76807 ,  H01L21/76816

Abstract: A method of forming vertical contacts in an integrated circuit that couple one or more metal lines in a given metallization level to first and second features occupying different levels in the integrated circuit comprises various processing steps. A first etch stop layer is formed overlying at least of portion of the first feature while a second etch stop layer is formed overlying at least a portion of the second feature. An ILD layer is formed overlying the first and second etch stop layers. A photolithographic mask is formed overlying the ILD layer. The photolithographic mask defines a first opening over the first feature and a second opening over the second feature. A first etch process etches a first hole in the ILD layer through the first opening in the photolithographic mask that lands on the first etch stop layer and etches a second hole in the ILD layer through the second opening that lands on the second etch stop layer. Subsequently, a second etch process further etches the first hole so that it lands on the first feature.

Abstract translation: 在集成电路中形成垂直触点的方法，其将给定金属化水平中的一个或多个金属线耦合到在集成电路中占据不同电平的第一和第二特征包括各种处理步骤。 形成第一蚀刻停止层，覆盖第一特征的至少一部分，而形成第二蚀刻停止层，覆盖第二特征的至少一部分。 形成覆盖在第一和第二蚀刻停止层上的ILD层。 在ILD层上形成光刻掩模。 光刻掩模限定第一特征上的第一开口和第二特征上的第二开口。 第一蚀刻工艺通过位于第一蚀刻停止层上的光刻掩模中的第一开口蚀刻ILD层中的第一孔，并通过第二开口蚀刻ILD层中的第二孔，该第二孔位于第二蚀刻停止层上。 随后，第二蚀刻工艺进一步蚀刻第一孔使其落在第一特征上。