公开(公告)号：US12164353B2

公开(公告)日：2024-12-10

申请号：US17936740

申请日：2022-09-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Shang Yang

IPC: G06F1/3206

Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

公开(公告)号：US20240406416A1

公开(公告)日：2024-12-05

申请号：US18206056

申请日：2023-06-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mark Thompson ,  Jonathan Philip Bonsor-Matthews

IPC: H04N19/172

Abstract: A processing unit (PU) is configured to generate reference values based on previously displayed frames in order to decode encoded frames having one or more noise-based effects. To this end, the PU includes a noise effect circuitry configured to determine noise values associated with a previously displayed frame. The noise effect circuitry then subtracts respective noise values from the pixel values of the previously displayed frame to determine reference values for decoding an encoded frame. Further, the PU includes a decoder that decodes the encoded frame based on the determined reference values.

公开(公告)号：US20240404897A1

公开(公告)日：2024-12-05

申请号：US18676665

申请日：2024-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Mihir PANDYA ,  Liwei WANG ,  Samuel NAFFZIGER

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.

公开(公告)号：US20240403121A1

公开(公告)日：2024-12-05

申请号：US18203360

申请日：2023-05-30

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Anil Harwani ,  Paul Blinzer ,  Kenneth Lawrence Mitchell ,  Adam Neil Calder Clark ,  Amitabh Mehra ,  Joshua Taylor Knight ,  Grant Evan Ley ,  Jerry Anton Ahrens ,  William Robert Alverson

IPC: G06F9/50

Abstract: Task scheduling based on component margins is described. In accordance with the described techniques, a scheduler of an operating system accesses a margin table when a request to perform tasks is received. The scheduler schedules tasks on various components of a system based on margins of those components. When a request to perform a task is received, for example, the scheduler accesses the margin table and selects a component to perform the task based on the margin information included in the margin table as well as based on the task, such as whether the task benefits more from being performed fast or being performed accurately. The scheduler then schedules the task using the selected component.

公开(公告)号：US12158842B2

公开(公告)日：2024-12-03

申请号：US17956995

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Benjamin Youngjae Cho ,  Armand Bahram Behroozi ,  Michael L. Chu ,  Ashwin Aji

IPC: G06F12/02 ,  G06F12/06

Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.

公开(公告)号：US20240394346A1

公开(公告)日：2024-11-28

申请号：US18201675

申请日：2023-05-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ahmet Artu Yildirim

IPC: G06F21/10 ,  G06F21/62

Abstract: A distributed processing system includes one or more accelerated units (AUs) connected to a network. To control access to the AUs by one or more users over the network, the distributed processing system includes a control plane circuitry connected to the network. The control plane circuitry is configured to grant a user access to one or more AUs connected to the network based on user security data stored at the control plane circuitry. The security data stored at the control plane circuitry indicates which resources of one or more AUs connected to the network one or more users are authorized to access.

公开(公告)号：US12154224B2

公开(公告)日：2024-11-26

申请号：US17033023

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jan H. Achrenius ,  Kiia Kallio ,  Miikka Kangasluoma ,  Ruijin Wu ,  Anirudh R. Acharya

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00

Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.

公开(公告)号：US12153927B2

公开(公告)日：2024-11-26

申请号：US16889010

申请日：2020-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Marius Evers ,  Aparna Mandke ,  Steven R. Havlir ,  Robert Cohen ,  Anthony Jarvis

IPC: G06F9/38 ,  G06F9/48

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

公开(公告)号：US12153926B2

公开(公告)日：2024-11-26

申请号：US18393657

申请日：2023-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Michael T. Clark ,  Marius Evers ,  William L. Walker ,  Paul Moyer ,  Jay Fleischman ,  Jagadish B. Kotra

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52

Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US12153922B2

公开(公告)日：2024-11-26

申请号：US18147075

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R Poremba ,  Ersin Cukurtas

IPC: G06F9/30 ,  G06F7/02

Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.