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公开(公告)号：US11960435B2
公开(公告)日：2024-04-16
申请号：US17692147
申请日：2022-03-10
发明人： Pradeep Jayaraman , Dean Gonzales , Gerald R. Talbot , Ramon A. Mangaser , Michael J. Tresidder , Prasant Kumar Vallur , Srikanth Reddy Gruddanti , Krishna Reddy Mudimela Venkata , David H. McIntyre
IPC分类号： G06F13/42 , H01L25/065
CPC分类号： G06F13/4291 , G06F13/4286 , H01L25/0652
摘要： A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.
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公开(公告)号：US20240119993A1
公开(公告)日：2024-04-11
申请号：US18390431
申请日：2023-12-20
IPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/06
CPC分类号： G11C11/4076 , G06F1/08 , G06F1/10 , G06F3/0604 , G06F3/0659 , G06F3/0671
摘要： A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.
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公开(公告)号：US20240119010A1
公开(公告)日：2024-04-11
申请号：US18380954
申请日：2023-10-17
发明人： Steven RAASCH , Andrew G. KEGEL
IPC分类号： G06F12/1009 , G06F9/50 , G06F11/07 , G06F12/02 , G06F12/0871 , G06F12/0882 , G06F12/1027 , G06F12/123
CPC分类号： G06F12/1009 , G06F9/5016 , G06F11/0772 , G06F12/0246 , G06F12/0871 , G06F12/0882 , G06F12/1027 , G06F12/123
摘要： A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.
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公开(公告)号：US11954036B2
公开(公告)日：2024-04-09
申请号：US17985674
申请日：2022-11-11
IPC分类号： G06F12/0862 , G06F8/41 , G06F9/52
CPC分类号： G06F12/0862 , G06F8/4442 , G06F9/52 , Y02D10/00
摘要： Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.
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公开(公告)号：US20240112747A1
公开(公告)日：2024-04-04
申请号：US17957808
申请日：2022-09-30
IPC分类号： G11C29/10
CPC分类号： G11C29/10
摘要： A memory controller includes a first arbiter for selecting memory commands for dispatch to a memory over a first channel, a second arbiter for selecting memory commands for dispatch to the memory over a second channel, and a test circuit. The test circuit generates a respective testing sequence of read commands and write commands for each of the first channel and second channel, and causes the testing sequences to be transmitted over the first and second channels at least partially overlapping in time without selection by the first or second arbiters.
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公开(公告)号：US20240112722A1
公开(公告)日：2024-04-04
申请号：US17957820
申请日：2022-09-30
IPC分类号： G11C11/4078 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/40615 , G11C11/40622
摘要： A memory controller for generating accesses for a memory includes a row hammer logic circuit for providing a sample request. In response to the sample request, the memory controller generates a sample command for dispatch to the memory to cause the memory to capture a current row. In response to a completion of the sample command, the memory controller generates a mitigation command for dispatch to the memory.
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公开(公告)号：US20240112720A1
公开(公告)日：2024-04-04
申请号：US17957788
申请日：2022-09-30
IPC分类号： G11C11/4076
CPC分类号： G11C11/4076
摘要： A memory system includes a PHY embodied on an integrated circuit, the PHY coupling to a memory over conductive traces on a substrate. The PHY includes a reference clock generation circuit providing a reference clock signal to the memory, a first group of driver circuits providing CA signals to the memory, and a second group of driver circuits providing DQ signals to the memory. A plurality of the conductive traces which carry the DQ signals are constructed with a length longer than that of conductive traces carrying the reference clock signal in order to reduce an effective insertion delay associated with coupling the reference clock signal to latch respective incoming DQ signals.
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公开(公告)号：US20240112392A1
公开(公告)日：2024-04-04
申请号：US17956567
申请日：2022-09-29
摘要： Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.
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公开(公告)号：US20240111684A1
公开(公告)日：2024-04-04
申请号：US17957479
申请日：2022-09-30
IPC分类号： G06F12/0897
CPC分类号： G06F12/0897 , G06F2212/601
摘要： The disclosed method includes detecting a stalled memory request, for a first level cache within a cache hierarchy of a processor, that includes an outstanding memory request associated with a second level cache within the cache hierarchy that is higher than the first level cache. The method further includes indicating, to the second level cache, that the first level cache is experiencing a starvation issue due to stalled memory requests to enable the second level cache to perform starvation-remediation actions. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US20240111683A1
公开(公告)日：2024-04-04
申请号：US17958179
申请日：2022-09-30
发明人： Amit Apte , Ganesh Balakrishnan
IPC分类号： G06F12/0895
CPC分类号： G06F12/0895 , G06F2212/60
摘要： A method includes, in a cache directory, storing a set of entries corresponding to one or more memory regions having a first region size when the cache directory is in a first configuration, and based on a workload sparsity metric, reconfiguring the cache directory to a second configuration. In the second configuration, each entry in the set of entries corresponds to a memory region having a second region size.
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