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    Memory controller having precharge prediction based on processor and PCI bus cycles
    72.
    发明授权
    Memory controller having precharge prediction based on processor and PCI bus cycles 有权
    存储器控制器具有基于处理器和PCI总线周期的预充电预测

    公开(公告)号：US5960459A

    公开(公告)日：1999-09-28

    申请号：US141702

    申请日：1998-08-28

    申请人： Gary W. Thome ,  Michael P. Moriarty ,  John E. Larson

    发明人： Gary W. Thome ,  Michael P. Moriarty ,  John E. Larson

    IPC分类号： G06F13/16 ,  G06F12/06

    CPC分类号： G06F13/1631

    摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

    摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

    Auto run apparatus, and associated method, for a convergent device
    74.
    发明授权
    Auto run apparatus, and associated method, for a convergent device 失效
    自动运行装置及相关方法，用于收敛装置

    公开(公告)号：US5954805A

    公开(公告)日：1999-09-21

    申请号：US828524

    申请日：1997-03-31

    申请人： Kevin J. Brusky ,  Derrill L. Sturgeon

    发明人： Kevin J. Brusky ,  Derrill L. Sturgeon

    IPC分类号： G06F9/445 ,  G06F13/14

    CPC分类号： G06F9/445

    摘要： Auto run apparatus, and an associated method, selectively permits execution of an auto run CD received at a CD ROM drive of a convergent device. When the auto run CD is received at the CD ROM drive, the operational mode of the convergent device is transferred to a computer mode. Thereafter, automatic execution of the CD is permitted.

    摘要翻译： 自动运行装置和相关联的方法，选择性地允许执行在收敛装置的CD ROM驱动器处接收的自动运行CD。 当在CD ROM驱动器上接收到自动运行的CD时，会聚装置的操作模式被转移到计算机模式。 此后，允许CD的自动执行。

    Memory controller including write posting queues, bus read control logic, and a data contents counter
    75.
    发明授权
    Memory controller including write posting queues, bus read control logic, and a data contents counter 失效
    存储器控制器包括写入寄存队列，总线读取控制逻辑和数据内容计数器

    公开(公告)号：US5938739A

    公开(公告)日：1999-08-17

    申请号：US811587

    申请日：1997-03-05

    申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F13/14

    CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

    摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

    摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

    Accelerated graphics port memory mapped status and control registers
    76.
    发明授权
    Accelerated graphics port memory mapped status and control registers 失效
    加速图形端口存储器映射状态和控制寄存器

    公开(公告)号：US5936640A

    公开(公告)日：1999-08-10

    申请号：US941862

    申请日：1997-09-30

    申请人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

    发明人： Ronald T. Horan ,  Phillip M. Jones ,  Gregory N. Santos ,  Robert Allan Lester ,  Robert C. Elliott

    IPC分类号： G06F3/14 ,  G06F12/10 ,  G06F15/00 ,  G06F12/06

    CPC分类号： G06F3/14 ,  G06F12/1027 ,  G06F12/1081

    摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

    摘要翻译： 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 多个AGP存储器映射状态和控制寄存器存储在计算机系统存储器中，用于计算机系统中AGP功能的状态和控制。

    Computer docking station with integral base security system
    77.
    发明授权
    Computer docking station with integral base security system 失效
    带基座安全系统的计算机对接站

    公开(公告)号：US5933322A

    公开(公告)日：1999-08-03

    申请号：US735673

    申请日：1996-10-23

    申请人： Mark H. Ruch ,  Steven S. Homer ,  Kelly K. Smith ,  Jason Q. Paulsel ,  Greangsak Jongolnee

    发明人： Mark H. Ruch ,  Steven S. Homer ,  Kelly K. Smith ,  Jason Q. Paulsel ,  Greangsak Jongolnee

    IPC分类号： G06F1/16 ,  H05K5/00 ,  H05K7/10

    CPC分类号： H05K5/0021 ,  G06F1/1632

    摘要： A computer docking station is provided which, in a disclosed embodiment thereof, includes multiple security features. The security features are operable to prevent access to interior portions of the docking station, prevent access to a card bay of the docking station, prevent ejection of a disk drive from a disk drive module of the docking station, and prevent operation of the disk drive module. Operation of the security features may be simultaneously and conveniently initiated by rotating a keyed lock mechanism to thereby rotate a cam mounted thereto.

    摘要翻译： 提供了一种计算机对接站，其在其公开的实施例中包括多个安全特征。 安全特征可操作以防止对接站的内部部分的访问，阻止访问对接站的卡槽，防止磁盘驱动器从对接站的磁盘驱动器模块的弹出，并且防止磁盘驱动器的操作 模块。 安全特征的操作可以通过旋转键锁定机构同时且方便地启动，从而旋转安装在其上的凸轮。

    Computer and computer network having a power down inhibit
    78.
    发明授权
    Computer and computer network having a power down inhibit 失效
    具有停电抑制功能的计算机和计算机网络

    公开(公告)号：US5925131A

    公开(公告)日：1999-07-20

    申请号：US699555

    申请日：1996-08-19

    申请人： Manuel Novoa ,  Robert S. Brayton

    发明人： Manuel Novoa ,  Robert S. Brayton

    IPC分类号： G06F1/26 ,  G06F1/00

    CPC分类号： G06F1/26

    摘要： The present invention relates to a computer network having a host computer and a plurality of user computers connected to the host computer by a computer network wherein the host computer can send a signal to inhibit any or all the user computers from completely powering down. More particularly, the present invention relates to a computer that can be inhibited from powering down when a user presses a power button. The computer may enter a standby state instead of powering down. Furthermore, the computer may inform the user that it is going to go into a standby state at a predetermined event after a power down inhibit signal is received from a host computer.

    摘要翻译： 本发明涉及一种计算机网络，其具有主计算机和通过计算机网络连接到主计算机的多个用户计算机，其中主计算机可发送信号以禁止任何或所有用户计算机完全断电。 更具体地，本发明涉及一种当用户按下电源按钮时可以禁止掉电的计算机。 计算机可能进入待机状态而不是掉电。 此外，在从主计算机接收到掉电禁止信号之后，计算机可以通知用户在预定事件中将进入待机状态。

    Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus
    79.
    发明授权
    Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus 失效
    在每个总线上具有总线主控器的计算机系统中仲裁访问第一和第二总线的双仲裁器

    公开(公告)号：US5923859A

    公开(公告)日：1999-07-13

    申请号：US974149

    申请日：1997-11-19

    申请人： Maria L. Melo ,  Robert Allan Lester

    发明人： Maria L. Melo ,  Robert Allan Lester

    IPC分类号： G06F13/364 ,  G06F13/00

    CPC分类号： G06F13/364

    摘要： Arbitration circuitry in a computer system having a plurality of arbiters for arbitrating requests from bus masters on a PCI bus and an EISA bus. Each of the PCI and EISA buses have a plurality of masters. The PCI bus utilizes a modified LRU arbitration scheme, while the EISA bus utilizes a rotating priority scheme. The arbiter on the EISA bus includes a first level of arbitration and a second level of arbitration. The first level is assigned a plurality of requester types to determine the priority between the requestor types. Certain of the first level requestor types include a plurality of devices. If one of those certain requestor types wins priority on the first level arbitration cycle, a second level arbitration is performed to determine the priority between the plurality of devices.

    摘要翻译： 具有用于在PCI总线和EISA总线上仲裁来自总线主机的请求的多个仲裁器的计算机系统中的仲裁电路。 每个PCI和EISA总线都有多个主机。 PCI总线使用修改的LRU仲裁方案，而EISA总线使用旋转优先级方案。 EISA总线上的仲裁员包括第一级仲裁和第二级仲裁。 为第一级分配了多个请求者类型以确定请求者类型之间的优先级。 某些第一级请求者类型包括多个设备。 如果这些某些请求者类型中的一个在第一级仲裁周期中赢得优先级，则执行第二级仲裁以确定多个设备之间的优先级。

    Expansion card insertion and removal
    80.
    发明授权
    Expansion card insertion and removal 失效
    扩充卡插拔

    公开(公告)号：US5922060A

    公开(公告)日：1999-07-13

    申请号：US775133

    申请日：1996-12-31

    申请人： Alan L. Goodrum

    发明人： Alan L. Goodrum

    IPC分类号： G06F13/40 ,  G06F13/00

    CPC分类号： G06F13/4081

    摘要： The invention features a circuit card for use with a computer system having a card slot electrically connected to a bus. The card slot has electrical contacts corresponding to lines of the bus. The circuit card has a first pin positioned to extend into the card slot when the card is inserted into the slot and contact a first electrical contact of the slot corresponding to a communication line of the bus. The circuit card also has a second pin positioned to extend into the card slot when the card is inserted into the slot and contact a second electrical contact of the slot corresponding to a clock line of the bus before the first pin contacts the first electrical contact.

    摘要翻译： 本发明的特征在于一种与具有与总线电连接的卡槽的计算机系统一起使用的电路卡。 卡槽具有对应于总线线路的电触点。 电路卡具有第一引脚，当卡插入到插槽中时，第一引脚被定位成延伸到卡插槽中，并且接触与总线的通信线相对应的槽的第一电触头。 当卡插入插槽中时，电路卡还具有一个第二引脚，该第二引脚定位成延伸到卡插槽中，并且在第一引脚与第一电触点接触之前，接触与总线的时钟线对应的插槽的第二电触头。