公开(公告)号：US06038624A

公开(公告)日：2000-03-14

申请号：US28711

申请日：1998-02-24

Applicant: Fu Chan ,  Kamran Khederzadeh ,  William C. Hallowell

Inventor： Fu Chan ,  Kamran Khederzadeh ,  William C. Hallowell

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4081

Abstract: A computer system in which various system peripherals are automatically re-initialized after being hot-swapped. The reinitialization includes accommodation of any required master/slave relationships between the peripherals.

Abstract translation: 一种计算机系统，其中各种系统外围设备在热交换后自动重新初始化。 重新初始化包括在外设之间调节任何所需的主/从关系。

公开(公告)号：US5946495A

公开(公告)日：1999-08-31

申请号：US838366

申请日：1997-04-08

Applicant: George J. Scholhamer ,  Michael S. Zandy

Inventor： George J. Scholhamer ,  Michael S. Zandy

IPC: G06F1/26 ,  G06F11/20 ,  H02J1/10 ,  G06F13/00 ,  H02J1/00

CPC classification number: G06F11/2015 ,  G06F1/263 ,  H02J1/10 ,  Y10T307/50

Abstract: In a computer system having redundant power supplies, an I.sup.2 C data bus architecture it utilized to provide communication between the power supplies and other computer peripherals connected to the I.sup.2 C bus. A switch separates the power supplies from the other peripheral devices, such that the switch, when open, isolates the power supplies from the other devices, so that during power-up the power supplies can communicate over the I.sup.2 C bus. When the switch is closed, the switch becomes transparent and connects the peripherals with the power supplies over the I.sup.2 C bus.

Abstract translation: 在具有冗余电源的计算机系统中，其用于提供电源和连接到I2C总线的其他计算机外围设备之间的通信的I2C数据总线架构。 开关将电源与其他外围设备分开，使得开关在打开时将电源与其他设备隔离开，以便在上电期间，电源可以通过I2C总线进行通信。 当交换机关闭时，交换机变得透明，并通过I2C总线将外围设备与电源连接。

公开(公告)号：US5937173A

公开(公告)日：1999-08-10

申请号：US873420

申请日：1997-06-12

Applicant: Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

Abstract translation: 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）的类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。

公开(公告)号：US5914730A

公开(公告)日：1999-06-22

申请号：US926421

申请日：1997-09-09

Applicant: Gregory N. Santos ,  Robert C. Elliott

Inventor： Gregory N. Santos ,  Robert C. Elliott

IPC: G06F12/08 ,  G06F3/14 ,  G06F12/10 ,  G06F13/36 ,  G06T11/00 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39 ,  G06F13/16

CPC classification number: G06F3/14 ,  G06F12/1081 ,  G09G5/39 ,  G06F12/1027 ,  G09G2360/121 ,  G09G2360/125 ,  G09G5/363

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. A GART cache entry control register is used by an application programming interface, such as a GART miniport driver, to indicate to the core logic chipset that an individual GART table entry in the chipset cache should be invalidated and/or updated. The core logic chipset may then perform the required invalidate and/or update operation on the individual GART table entry without having to flush or otherwise disturb the other still relevant GART table entries stored in the cache.

Abstract translation: 具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。 核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。 GART缓存条目控制寄存器由应用程序编程接口（如GART微型端口驱动程序）用于向核心逻辑芯片组指出芯片组缓存中的单个GART表条目应无效和/或更新。 核心逻辑芯片组然后可以对单独的GART表条目执行所需的无效和/或更新操作，而不必刷新或以其它方式干扰存储在高速缓存中的其他仍然相关的GART表条目。

公开(公告)号：US5905497A

公开(公告)日：1999-05-18

申请号：US828525

申请日：1997-03-31

Applicant: Mark P. Vaughan ,  Derrill L. Sturgeon ,  Christopher A. Howard ,  Kevin J. Brusky

Inventor： Mark P. Vaughan ,  Derrill L. Sturgeon ,  Christopher A. Howard ,  Kevin J. Brusky

IPC: G06F3/033 ,  G06F3/048 ,  H04N21/462 ,  G09G5/08 ,  G06F3/14

CPC classification number: G06F3/0482 ,  H04N21/4622

Abstract: A computer system has a computer display with two methods of navigation: discrete and continuous. In discrete navigation, a cursor is moved discretely using a set of arrow keys while in the continuous navigation, a pointer or other screen object has analog movement to any position on the screen using a trackball or other device. When the discrete navigational method is used to highlight a menu item in a menu on a computer display, the computer system masks the display of the pointer until re-activation of the pointer in the second navigational method. In addition, the computer system recalculates the location of the pointer to a position in the center of the highlighted menu item.

Abstract translation: 计算机系统具有具有两种导航方式的计算机显示器：离散和连续的。 在离散导航中，使用一组箭头键离开移动光标，而在连续导航中，指针或其他屏幕对象使用轨迹球或其他设备模拟移动到屏幕上的任何位置。 当使用离散导航方法突出显示计算机显示器上的菜单中的菜单项时，计算机系统屏蔽指针的显示，直到在第二导航方法中重新激活指针。 此外，计算机系统重新计算指针位置到突出显示的菜单项的中心位置。

公开(公告)号：US5892964A

公开(公告)日：1999-04-06

申请号：US885062

申请日：1997-06-30

Applicant: Ronald Timothy Horan ,  Gary W. Thome ,  Sompong Olarig

Inventor： Ronald Timothy Horan ,  Gary W. Thome ,  Sompong Olarig

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027 ,  G06F13/385

Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port ("AGP") bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect ("PCI") device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request ("REQ") and Grant ("GNT") signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

公开(公告)号：US5892933A

公开(公告)日：1999-04-06

申请号：US829202

申请日：1997-03-31

Applicant: Christopher D. Voltz

Inventor： Christopher D. Voltz

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4018

Abstract: A segmenting scheme and arrangement for digital serial busses such as an I.sup.2 C bus is provided. The segments are broken apart from the master unit by a switch such as a low-impedance bidirectional analog multiplexer. The bus may be of various types such as an I.sup.2 C, a Universal Serial Bus or other similar types of busses. The bus is bidirectional from the various slave or downstream units to the master unit and the various slave devices can operate at different speeds by allowing each segment to adjust the speed of that segment.

Abstract translation: 提供了诸如I2C总线的数字串行总线的分段方案和装置。 这些段通过诸如低阻抗双向模拟多路复用器之类的开关与主单元分开。 总线可以是各种类型的，例如I2C，通用串行总线或其他类似类型的总线。 总线从各个从机或下游单元到主单元是双向的，并且各个从设备可以通过允许每个段调整该段的速度以不同的速度操作。

公开(公告)号：US5867645A

公开(公告)日：1999-02-02

申请号：US723767

申请日：1996-09-30

Applicant: Sompong Paul Olarig

Inventor： Sompong Paul Olarig

IPC: G06F13/00 ,  G06F11/20 ,  G06F11/00

CPC classification number: G06F11/2007 ,  G06F2201/85

Abstract: A computer system having an interconnection apparatus for interconnecting processors, peripherals, and memories, including a bus structure with an extended-bus portion and a non-extended-bus portion, and the extended-bus-compliant devices having a status register. The extended-bus-compliant devices are operable in either extended-bus mode involving both the extended-bus portion and non-extended-bus portion of the bus structure, or non-extended-bus mode involving only the non-extended-bus portion. Upon detecting a transmission error or device-related fault, the contents of the status register are altered so as to render the extended-bus-compliant devices operable in the non-extended-bus mode using only the non-extended-bus portion.

Abstract translation: 具有用于互连处理器，外围设备和存储器的互连装置的计算机系统，包括具有扩展总线部分的总线结构和非扩展总线部分，以及具有状态寄存器的扩展总线兼容装置。 扩展总线兼容设备可以以涉及总线结构的扩展总线部分和非扩展总线部分的扩展总线模式操作，或者仅涉及非扩展总线部分的非扩展总线模式 。 在检测到传输错误或与设备有关的故障时，状态寄存器的内容被改变，以便仅使用非扩展总线部分使得扩展总线兼容的设备在非扩展总线模式下可操作。

公开(公告)号：US5857086A

公开(公告)日：1999-01-05

申请号：US855401

申请日：1997-05-13

Applicant: Ronald Timothy Horan ,  Sompong Paul Olarig

Inventor： Ronald Timothy Horan ,  Sompong Paul Olarig

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/385 ,  G06F13/4027

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of a PCI device connected to the common bus.

Abstract translation: 在可以被配置为加速图形端口（“AGP”）总线与主机和存储器总线之间的桥的计算机系统中提供了多用途核心逻辑芯片组，作为32位附加外围组件互连 “PCI”）总线和主机和存储器总线，或作为主PCI总线和附加PCI总线之间的桥梁。 多用芯片组的功能是在计算机系统制造时或在现场确定是否实现AGP总线桥接器或额外的32位PCI总线桥接器的功能。 多用核心逻辑芯片组具有对在附加32位PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线的仲裁器。 可以通过硬件信号输入，计算机系统配置或上电自检（“POST”）期间的软件来选择多用途核心逻辑芯片组中的总线桥（AGP或PCI）类型。 在检测到连接到公共总线的PCI设备时也可以确定软件配置。

公开(公告)号：US5857074A

公开(公告)日：1999-01-05

申请号：US695827

申请日：1996-08-16

Applicant: Derrick W. Johnson

Inventor： Derrick W. Johnson

IPC: G06F13/00 ,  G06F11/273 ,  G06F11/34 ,  H04L29/06

CPC classification number: G06F11/2294 ,  G06F11/0709 ,  G06F11/0748 ,  H04L29/06 ,  H04L69/18

Abstract: A communication system is presented whereby sequences of video screens sent from a host CPU to a video controller can be stored and subsequently retrieved by a terminal located remote from the host CPU. The host CPU and video controller form part of a server arranged within a distributed computing system. An administrator situated at the remote terminal can retrieve select video screens produced during server operations to determine information regarding the server configuration and possible causes of server failure or future failure. The sequence of video screens thereby represent video screen changes stored upon a server controller adapted for coupling to the server expansion bus. The video screen changes represent a sequence of video screen changes occurring prior to server failure or after server reset. Those changes provide beneficial information to an administrator located remote from the server, and allows the administrator to communicate with the server using several possible communication protocols. The server controller snoops display data written from the host CPU to the video controller and mirrors the display data upon buffers within the server controller. Information within the buffers can be called upon by a remotely situated administrator regardless of whether server power is lost in the interim.

Abstract translation: 提供了一种通信系统，其中从主机CPU发送到视频控制器的视频屏幕序列可以被存储并且随后由位于远离主机CPU的终端检索。 主机CPU和视频控制器构成分布式计算系统中安排的服务器的一部分。 位于远程终端的管理员可以检索在服务器操作期间产生的选择视频屏幕，以确定有关服务器配置的信息以及服务器故障或将来故障的可能原因。 因此，视频屏幕的顺序表示存储在适于耦合到服务器扩展总线的服务器控制器上的视频屏幕改变。 视频屏幕更改表示在服务器故障之前或服务器重置后发生的视频屏幕更改的序列。 这些更改为位于远离服务器的管理员提供有益的信息，并允许管理员使用几种可能的通信协议与服务器进行通信。 服务器控制器将从主机CPU写入的数据显示给视频控制器，并在服务器控制器中的缓冲区上镜像显示数据。 缓冲区内的信息可由远程管理员调用，无论是否在过渡期间服务器功耗丢失。