公开(公告)号：US07548128B2

公开(公告)日：2009-06-16

申请号：US11612666

申请日：2006-12-19

Applicant: Ray Rosik ,  Weinan Gao ,  Mats Lindstrom

Inventor： Ray Rosik ,  Weinan Gao ,  Mats Lindstrom

IPC: H03B5/32

CPC classification number: H03B5/06 ,  H03B5/364 ,  H03L3/00

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract translation: 提供了系统和方法。 在这方面，代表性系统包括晶体振荡器电路和数字自动电平控制电路。 数字自动电平控制电路用于：将晶体振荡器电路的振荡幅度转换为比例直流电压; 将DC电压转换为相应的数字代码表示; 并调整偏置电流和振荡器环路增益，使得设置期望的振荡幅度。

公开(公告)号：US07522010B2

公开(公告)日：2009-04-21

申请号：US11797081

申请日：2007-04-30

Applicant: Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

Inventor： Kevin YiKai Liang ,  Arvind Bomdica ,  Min Xu ,  Ming So

IPC: H03C1/00

CPC classification number: H03B5/364 ,  H03B2200/0082

Abstract: An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.

Abstract translation: 一种超低功耗晶体振荡器架构，在稳态运行期间吸收小于2μA。 放大器级是自偏置的，并具有限制其信号摆幅的输入和输出钳位电路。 选择电路值，使得第一放大器级有足够的瞬态负载电流进行振荡，同时输入和输出钳位电路保持级的足够低的摆幅，使得稳态平均负载电流在 小于1亩。

公开(公告)号：US07515895B2

公开(公告)日：2009-04-07

申请号：US11050107

申请日：2005-02-04

Applicant: Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

Inventor： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr

IPC: H04B1/10

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US20080284533A1

公开(公告)日：2008-11-20

申请号：US12185320

申请日：2008-08-04

Applicant: Sven Mattisson

Inventor： Sven Mattisson

IPC: H03B5/36

CPC classification number: H03B5/364

Abstract: An electrical oscillator circuit comprising: a resonator comprised in the first subcircuit; and an active device comprised in the second subcircuit connected to energize the resonator to provide an oscillating electrical signal transmitted as a differential signal via electrical conductors to the second subcircuit. The oscillator is characterized in that the second subcircuit comprises means for receiving the differential signal transmitted via the electrical conductors and converting the differential signal to a single-ended signal with reference to the signal ground reference of the second subcircuit. Thereby a noise robust oscillator signal is provided with the use of very few components. Particularly suitable for oscillators embodied in an integrated circuit with the resonator mounted on a printed circuit board, PCB. And an integrated circuit.

Abstract translation: 一种电振荡器电路，包括：包括在所述第一子电路中的谐振器; 以及包括在所述第二子电路中的有源器件，其连接用于激励所述谐振器，以将经由电导体发送的差分信号的振荡电信号提供给所述第二子电路。 振荡器的特征在于，第二分支电路包括用于接收通过电导体发送的差分信号的装置，并且参考第二子电路的信号接地参考将差分信号转换成单端信号。 因此，使用非常少的组件来提供噪声鲁棒振荡器信号。 特别适用于具有安装在印刷电路板，PCB上的谐振器的集成电路中的振荡器。 和一个集成电路。

公开(公告)号：US07391279B2

公开(公告)日：2008-06-24

申请号：US11430952

申请日：2006-05-10

Applicant: Masaaki Kamiya

Inventor： Masaaki Kamiya

IPC: H03B5/32

CPC classification number: H03B5/368 ,  H03B5/364 ,  H03B2200/0012

Abstract: A bypass capacitance is connected to a node between first and second self-bias resistances connected in series between an input and an output of an inverter. The bypass capacitance accommodates changes in the output voltage of the inverter to suppress the feedback effect from the output side to the input side of the inverter. That is, the bypass capacitance plays the role of suppressing a decrease in the input impedance by the Miller effect.

Abstract translation: 旁路电容连接到在逆变器的输入和输出之间串联连接的第一和第二自偏压之间的节点。 旁路电容适应变频器的输出电压的变化，以抑制从逆变器的输出侧到输入侧的反馈效应。 也就是说，旁路电容起到通过米勒效应抑制输入阻抗的降低的作用。

公开(公告)号：US20080143452A1

公开(公告)日：2008-06-19

申请号：US11612666

申请日：2006-12-19

Applicant: Ray Rosik ,  Weinan Gao ,  Mats Lindstrom

Inventor： Ray Rosik ,  Weinan Gao ,  Mats Lindstrom

IPC: H03B5/32

CPC classification number: H03B5/06 ,  H03B5/364 ,  H03L3/00

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract translation: 提供了系统和方法。 在这方面，代表性系统包括晶体振荡器电路和数字自动电平控制电路。 数字自动电平控制电路用于：将晶体振荡器电路的振荡幅度转换为比例直流电压; 将DC电压转换为相应的数字代码表示; 并调整偏置电流和振荡器环路增益，使得设置期望的振荡幅度。

公开(公告)号：US20080042769A1

公开(公告)日：2008-02-21

申请号：US11461120

申请日：2006-07-31

Applicant: Michael Berens

Inventor： Michael Berens

IPC: H03L7/099

CPC classification number: H03F1/3205 ,  H03B5/364 ,  H03F1/0261 ,  H03F1/301 ,  H03F3/345 ,  H03F2200/114 ,  H03F2200/357 ,  H03F2200/42

Abstract: Embodiments of the invention provide a low-power, high-gain amplifier for a crystal oscillator. In some embodiments, the oscillator amplifier circuit comprises two NMOS transistors stacked in series with a PMOS transistor. In various embodiments, each of the NMOS transistors is diode-connected through a resistor and has the input signal capacitively coupled onto its control terminal. The stacked amplifier raises the DC level of the amplified oscillatory signal and can support a substantial oscillation amplitude without clipping.

Abstract translation: 本发明的实施例提供了一种用于晶体振荡器的低功率高增益放大器。 在一些实施例中，振荡器放大器电路包括与PMOS晶体管串联堆叠的两个NMOS晶体管。 在各种实施例中，每个NMOS晶体管通过电阻二极管连接，并且具有电容耦合到其控制端上的输入信号。 堆叠放大器提高放大的振荡信号的直流电平，并且可以支持实质的振荡幅度而不会削波。

公开(公告)号：US07276970B2

公开(公告)日：2007-10-02

申请号：US11131281

申请日：2005-05-18

Applicant: Haideh Khorramabadi

Inventor： Haideh Khorramabadi

IPC: H03F3/45

CPC classification number: H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03F1/3211 ,  H03F1/52 ,  H03F3/191 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/294 ,  H03F2203/45318 ,  H03F2203/45704 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/18 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. The filters incorporate a gain stage that provides improved dynamic range through the use of cross coupled auxiliary differential pair CMOS amplifiers to cancel distortion in a main linearized differential pair amplifier. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.滤波器包括增益级，其通过使用交叉耦合辅助差分对CMOS放大器来消除主线性化差分对放大器中的失真而提供改进的动态范围。 频率规划提供额外的镜像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US07132888B2

公开(公告)日：2006-11-07

申请号：US10809838

申请日：2004-03-26

Applicant: Arya R. Behzad

Inventor： Arya R. Behzad

IPC: H03F3/45

CPC classification number: H03F1/3211 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0026 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/364 ,  H03B2201/025 ,  H03B2201/0266 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L1/023 ,  H03L7/10 ,  H03L7/23 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection is substantially implemented on a single CMOS integrated circuit. A receiver front end provides programable attenuation and a programable gain low noise amplifier. LC filters integrated onto the substrate in conjunction with image reject mixers provide image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. Active filters utilize multi track spiral inductors with shields to increase circuit Q. Frequency planning provides additional image rejection. Local oscillator signal generation methods on chip reduce distortion. A PLL generates needed out of band LO signals. Direct synthesis generates in band LO signals. PLL VCOs are centered automatically. A differential crystal oscillator provides a frequency reference. Differential signal transmission throughout the receiver is used. ESD protection is provided by a pad ring and ESD clamping structure. Shunts utilize a gate boosting at each pin to discharge ESD build up. An IF VGA utilizes distortion cancellation achieved with cross coupled differential pair amplifiers having their Vds dynamically modified in conjunction with current steering of the differential pairs sources.

Abstract translation: 具有通道选择和图像抑制的集成接收器基本上在单个CMOS集成电路上实现。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 与图像抑制混合器一起集成到衬底上的LC滤波器提供图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 有源滤波器利用具有屏蔽的多轨螺旋电感器来增加电路Q.频率规划提供额外的图像抑制。 本地振荡器信号产生方法在芯片上减少失真。 PLL产生所需的带外LO信号。 直接合成产生带内LO信号。 PLL VCO自动居中。 差分晶体振荡器提供频率参考。 使用整个接收机的差分信号传输。 ESD保护由衬垫环和ESD夹紧结构提供。 分流器利用每个引脚上的门极升压来放电ESD积聚。 IF VGA利用交叉耦合的差分对放大器实现的失真消除，其具有与差分对源的当前转向结合动态修改的V ds。

公开(公告)号：US20060208817A1

公开(公告)日：2006-09-21

申请号：US11375678

申请日：2006-03-14

Applicant: Tomio Satoh

Inventor： Tomio Satoh

IPC: H03B5/32

CPC classification number: H03K3/0307 ,  H03B5/364 ,  H03B5/368 ,  H03B2200/0098

Abstract: A piezoelectric oscillator includes an inverter amplifier, a first load impedance constituting together with the inverter amplifier a connection circuit that is inserted between the power supply and the ground, a piezoelectric resonator being inserted between the input of the inverter amplifier and the ground, a second load impedance being serially inserted and connected between the input of the inverter amplifier and a connecting point of the inverter amplifier and the first load impedance, and a resistor being connected between the input and an output of the inverter amplifier.

Abstract translation: 压电振荡器包括反相放大器，与反相放大器一起构成的第一负载阻抗，插入在电源和地之间的连接电路，压电谐振器插入在反相放大器的输入端和地之间;第二负载阻抗 负载阻抗串联插入并连接在反相放大器的输入端和反相放大器的连接点与第一负载阻抗之间，电阻器连接在反相放大器的输入端和输出端之间。