公开(公告)号：US20100329019A1

公开(公告)日：2010-12-30

申请号：US12874687

申请日：2010-09-02

Applicant: Toshio MUKUNOKI

Inventor： Toshio MUKUNOKI

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C7/08 ,  G11C7/1042 ,  G11C7/12 ,  G11C16/0475

Abstract: When data is read from a memory cell of a top array block to a bit line, a switching device is closed so that the data is stored in the form of electrical charges at a bit line of a bottom array block. The switching device at a top array side is opened to drive a sense amplifier, and thus, the data read from the memory cell and retained at the bit line of the bottom array block is output to the outside. While the data is output in the above-described manner, a potential of the bit line of the top array block can be precharged to start a next read operation.

Abstract translation: 当将数据从顶部阵列块的存储单元读取到位线时，关闭开关装置，使得数据以底部阵列块的位线的电荷形式存储。 打开顶部阵列侧的开关装置以驱动读出放大器，从而从存储器单元读取并保留在底部阵列块的位线处的数据被输出到外部。 当以上述方式输出数据时，顶部阵列块的位线的电位可以被预充电以开始下一次读取操作。

公开(公告)号：US07855114B2

公开(公告)日：2010-12-21

申请号：US12351553

申请日：2009-01-09

Applicant: Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

Inventor： Wei Zheng ,  Mark Randolph ,  Hidehiko Shiraiwa

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/792 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282

Abstract: A memory device may include a source region and a drain region formed in a substrate and a channel region formed in the substrate between the source and drain regions. The memory device may further include a first oxide layer formed over the channel region, the first oxide layer having a first dielectric constant, and a charge storage layer formed upon the first oxide layer. The memory device may further include a second oxide layer formed upon the charge storage layer, a layer of dielectric material formed upon the second oxide layer, the dielectric material having a second dielectric constant that is greater than the first dielectric constant, and a gate electrode formed upon the layer of dielectric material.

Abstract translation: 存储器件可以包括形成在衬底中的源极区域和漏极区域以及形成在源极和漏极区域之间的衬底中的沟道区域。 存储器件还可以包括形成在沟道区上的第一氧化物层，第一氧化物层具有第一介电常数，以及形成在第一氧化物层上的电荷存储层。 存储器件还可以包括形成在电荷存储层上的第二氧化物层，形成在第二氧化物层上的介电材料层，介电材料具有大于第一介电常数的第二介电常数，以及栅电极 形成在电介质材料层上。

公开(公告)号：US07830713B2

公开(公告)日：2010-11-09

申请号：US12075677

申请日：2008-03-13

Applicant: Peter Wung Lee ,  Fu-Chang Hsu

Inventor： Peter Wung Lee ,  Fu-Chang Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/0483 ,  G11C16/10 ,  H01L29/7887 ,  H01L29/7923

Abstract: A nonvolatile memory structure with pairs of serially connected select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the serially connected select transistors has an implant to make a threshold voltage of the implanted first serially connected select transistor different from a non-implanted second serially connected select transistor. The pair of serially connected top select transistors is connected to a first of two associated bit lines. Optionally, the NAND nonvolatile memory strings further is connected a pair of serially connected bottom select transistors that is connected to the second associated bit line.

Abstract translation: 一种具有串联连接的选择晶体管的非易失性存储器结构，其连接到双面电荷捕获非易失性存储器单元的NAND组串列的顶部和可选地到底部，用于控制NAND串联到相关位线的连接 。 串联连接的选择晶体管中的第一个具有植入物，以使得注入的第一串联选择晶体管的阈值电压不同于未注入的第二串联选择晶体管。 一对串联连接的顶部选择晶体管连接到两个相关位线中的第一个。 可选地，NAND非易失性存储器串还连接有连接到第二相关位线的一对串联连接的底部选择晶体管。

公开(公告)号：US07829938B2

公开(公告)日：2010-11-09

申请号：US11181345

申请日：2005-07-14

Applicant: Arup Bhattacharyya

Inventor： Arup Bhattacharyya

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0475 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/42336 ,  H01L29/513 ,  H01L29/7881

Abstract: Non-volatile memory devices and arrays are described that utilize dual gate (or back-side gate) non-volatile memory cells with band engineered gate-stacks that are placed above or below the channel region in front-side or back-side charge trapping gate-stack configurations in NAND memory array architectures. The band-gap engineered gate-stacks with asymmetric or direct tunnel barriers of the floating node memory cells of embodiments of the present invention allow for low voltage tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The memory cell architecture also allows for improved high density memory devices or arrays with the utilization of reduced feature word lines and vertical select gates.

Abstract translation: 描述了利用双栅极（或背侧栅极）非易失性存储器单元的非易失性存储器件和阵列，其具有放置在前侧或后侧电荷俘获中的沟道区域的上方或下方的带工程化栅极堆叠 NAND存储器阵列架构中的栅极堆叠配置。 具有本发明实施例的浮动节点存储器单元的不对称或直接隧道势垒的带隙工程化栅极堆栈允许低电压隧道编程和电子和空穴的有效擦除，同时保持高电荷阻挡屏障和深载流子俘获 网站保持良好的电荷。 存储单元架构还允许利用减少的特征字线和垂直选择栅极的改进的高密度存储器件或阵列。

公开(公告)号：US20100259984A1

公开(公告)日：2010-10-14

申请号：US12752573

申请日：2010-04-01

Applicant: Hidenori TAKEUCHI

Inventor： Hidenori TAKEUCHI

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/14

Abstract: An erase method of a nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first insulating layer, a charge accumulation layer formed in a second area on the first insulating layer, a second insulating layer formed on the charge accumulation layer and a second gate electrode formed on the second insulating layer includes a step of injecting hot holes into the charge accumulation layer from the diffusion region and a step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side.

Abstract translation: 一种非易失性半导体存储器件的擦除方法，包括具有彼此间隔开的扩散区域的半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的第一区域中的第一栅极电极，电荷累积层 形成在第一绝缘层上的第二区域中，形成在电荷累积层上的第二绝缘层和形成在第二绝缘层上的第二栅电极包括从扩散区向电荷累积层注入热孔的步骤，以及 将通道热电子注入靠近第一栅电极侧的电荷累积层的一部分的步骤。

公开(公告)号：US07813169B2

公开(公告)日：2010-10-12

申请号：US12016774

申请日：2008-01-18

Applicant: Andreas Kux ,  Detlev Richter

Inventor： Andreas Kux ,  Detlev Richter

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/16 ,  G11C29/02 ,  G11C29/028 ,  G11C29/12005 ,  G11C2029/0407

Abstract: Disclosed embodiments relate to integrated circuits, a method to operate an integrated circuit, and a method to determine an electrical erase sequence. More particularly, the application relates to devices having at least two memory cells and methods relating to its operation.

Abstract translation: 公开的实施例涉及集成电路，操作集成电路的方法以及确定电擦除序列的方法。 更具体地，本申请涉及具有至少两个存储器单元的装置和与其操作有关的方法。

公开(公告)号：US07808818B2

公开(公告)日：2010-10-05

申请号：US11646395

申请日：2006-12-28

Applicant: Boaz Eitan

Inventor： Boaz Eitan

IPC: G11C16/04

CPC classification number: H01L29/7923 ,  G11C16/0475 ,  H01L29/66833

Abstract: Secondary electron injection (SEI) is used for programming NVM cells having separate charge storage areas in an ONO layer, such as NROM cells. Various combinations of low wordline voltage (Vwl), negative substrate voltabe (Vb), and shallow and deep implants facilitate the process. Second bit problems may be controlled, and retention and punchthrough may be improved. Lower SEI programming current may result in relaxed constraints on bitine resistance, number of contacts required, and power supply requirements.

Abstract translation: 二次电子注入（SEI）用于编程在ONO层中具有分离的电荷存储区域的NVM单元，例如NROM单元。 低字线电压（Vwl），负底片伏特（Vb）和浅层和深层植入物的各种组合有利于该过程。 可以控制第二位问题，并且可以提高保持和穿透。 较低的SEI编程电流可能会导致对苦味电阻，所需接触数量和电源要求的放宽限制。

公开(公告)号：US07746706B2

公开(公告)日：2010-06-29

申请号：US11639935

申请日：2006-12-15

Applicant: Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

Inventor： Nian Yang ,  Yonggang Wu ,  Tien-Chun Yang

IPC: G11C16/04

CPC classification number: G11C16/3404 ,  G11C16/0475

Abstract: One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.

Abstract translation: 本发明的一个实施例涉及访问存储器单元的方法。 在该方法中，擦除存储单元的至少一位。 在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。 还公开了其它方法和系统。

公开(公告)号：US07746694B2

公开(公告)日：2010-06-29

申请号：US11775107

申请日：2007-07-09

Applicant: Yi Ying Liao

Inventor： Yi Ying Liao

IPC: G11C16/04

CPC classification number: G11C16/0475 ,  G11C16/10

Abstract: The technology relates to nonvolatile memory with a modified channel region interface, such as a raised source and drain or a recessed channel region.

Abstract translation: 该技术涉及具有改进的通道区域界面的非易失性存储器，例如升高的源极和漏极或凹陷沟道区域。

公开(公告)号：US07742339B2

公开(公告)日：2010-06-22

申请号：US12087594

申请日：2007-01-10

Applicant: Arik Rizel ,  Guy Cohen

Inventor： Arik Rizel ,  Guy Cohen

IPC: G11C16/00

CPC classification number: G11C16/0475 ,  G11C16/26

Abstract: Selecting a read voltage level for a NVM cell by using an initial value for the read voltage and performing a read operation, comparing an actual number of bits found to an expected number of bits and, if there is a discrepancy between the actual number and the expected number, adjusting the read voltage level, based on variable data such as statistics available, level occupation, neighbor level, previous chunks data, and other data used during read, program or erase. For example, based on a number of missing bits, or upon a result of a previous read operation, or a result obtained at another program level, or upon how many times the memory cell has been cycled, or upon how many memory cells are at each program level, or on a number of bits at another program level in a selected chunk of memory.

Abstract translation: 通过使用读取电压的初始值并执行读取操作来选择NVM单元的读取电压电平，将发现的实际位数与预期位数进行比较，如果实际数字与 基于可用数据，如可用统计数据，级别占用，邻居级别，先前块数据以及在读取，编程或擦除期间使用的其他数据的可变数据来调整读取电压电平。 例如，基于多个丢失比特，或者基于先前读取操作的结果，或者在另一程序级别获得的结果，或者存储器单元已循环多少次，或者存储器单元处于多少 每个节目级别，或者在所选择的存储器块中的另一程序级别的多个位上。