公开(公告)号：US5606520A

公开(公告)日：1997-02-25

申请号：US484540

申请日：1995-06-07

Applicant: Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

Inventor： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

IPC: G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F7/38 ,  G06F12/00

CPC classification number: G06F15/17375 ,  G06F12/0284

Abstract: A data processing address generator includes a plurality of address registers, a plurality of index address registers, a modulo register storing a plurality of carry break indicators and an arithmetic unit. The arithmetic unit adds or subtracts a selected address register and a selected index register. The arithmetic unit generates a normal carry between a particular bit and the next more significant bit if a corresponding carry break indicator stored in said modulo register has a first digital state. The arithmetic unit breaks any carry between the particular bit and the next more significant bit if the corresponding carry break indicator has a second digital state. The carry break may be dependent upon a modulo qualifier bit being in an enabling state. The modulo qualifier bit may be stored in one of a plurality of qualifier registers corresponding to the address registers.

Abstract translation: 数据处理地址生成器包括多个地址寄存器，多个索引地址寄存器，存储多个进位断点指示符的模数寄存器和运算单元。 算术单元增加或减少选定的地址寄存器和选定的索引寄存器。 如果存储在所述模数寄存器中的对应进位断点指示符具有第一数字状态，则运算单元在特定位和下一更高有效位之间产生正常进位。 如果相应的进位断点指示符具有第二数字状态，运算单元将特定位和下一个更高有效位之间的任何进位断开。 进位中断可以取决于模数限定位位于使能状态。 模数限定符位可以存储在与地址寄存器对应的多个限定符寄存器之一中。

公开(公告)号：US5559970A

公开(公告)日：1996-09-24

申请号：US237843

申请日：1994-05-04

Applicant: Vinod Sharma

Inventor： Vinod Sharma

IPC: G06F13/14 ,  G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  H04Q11/04 ,  G06F13/00

CPC classification number: H04Q11/0478 ,  G06F15/17375 ,  H04L49/253 ,  H04L49/101 ,  H04L49/3018 ,  H04L49/40

Abstract: A self-routing crossbar switch interconnects a plurality of processors with a plurality of memory modules. In a self-routing crossbar switch connecting N processors and N memory modules, a processor is connected to each input port and a memory module is connected to each output port; each of the N processors can transmit a memory request simultaneously provided that there is no port contention and no bank contention. Port contention occurs if two or more processors attempt to access the same output port of the self-routing crossbar switch at the same time. The memory module consists of several memory banks that are connected in an interleaved manner. If the memory bank is accessed before it is ready to accept a new request, bank contention is said to have occurred. In the self-routing crossbar switch the requests directed to a port are first passed through an aligner and a conflict resolution logic. There is one aligner associated with each output port. The aligner inputs the requests directed at an output port and aligns them so that, at the output of the aligner, all the active requests appear in a consecutive fashion. The conflict resolution logic resolves the port and bank contention.

Abstract translation: 自路由交叉开关将多个处理器与多个存储器模块互连。 在连接N个处理器和N个存储器模块的自路由交叉开关中，处理器连接到每个输入端口，并且存储器模块连接到每个输出端口; N个处理器中的每一个可以同时发送存储器请求，只要没有端口争用并且没有银行争用。 如果两个或多个处理器同时尝试访问自路由交叉开关的相同输出端口，则会发生端口争用。 存储器模块由以交错方式连接的多个存储体组成。 如果在准备好接受新请求之前存储存储器被访问，则认为银行争用已经发生。 在自路由交叉开关中，引导到端口的请求首先通过对齐器和冲突解决逻辑。 每个输出端口都有一个对齐器。 对准器输入针对输出端口的请求并对齐它们，使得在对齐器的输出处，所有活动请求以连续的方式出现。 冲突解决逻辑解决了港口和银行的争论。

公开(公告)号：US5530813A

公开(公告)日：1996-06-25

申请号：US285916

申请日：1994-08-04

Applicant: Mark T. Paulsen ,  Steven W. Tonkin

Inventor： Mark T. Paulsen ,  Steven W. Tonkin

IPC: G06F13/40 ,  G06F15/173 ,  G06F13/00

CPC classification number: G06F15/17375 ,  G06F13/4022

Abstract: Method and apparatus for using a field-programmable gate-array circuit as a crossbar switch. In order to connect a first port of the crossbar switch to a second port, an address within the field-programmable gate-array circuit is calculated, and a first data pattern to load at that address is determined. A second data pattern to load at that address is determined in order to disconnect the first port from the second port. The first port is then connected to the second port by loading the first data pattern at the calculated address in the field-programmable gate-array circuit. Subsequently the first port is disconnected from the second port by loading the second data pattern at the calculated address in the field-programmable gate-array circuit. Mechanisms are provided for analog or digital ports, for multiple-bit digital ports, for combinations of logical functions with the crossbar-switch functions, and for latching the data within the crossbar switch. In one embodiment, the crossbar switch is incrementally reconfigurable wherein ports not involved in the reconfiguration are not affected by the reconfiguration operation. Applications to machine vision systems are described.

Abstract translation: 使用现场可编程门阵列电路作为交叉开关的方法和装置。 为了将交叉开关的第一端口连接到第二端口，计算现场可编程门阵列电路内的地址，并且确定在该地址处加载的第一数据模式。 确定在该地址处加载的第二数据模式，以便将第一端口与第二端口断开连接。 然后通过在现场可编程门阵列电路中的计算地址处加载第一数据模式将第一端口连接到第二端口。 随后，通过在现场可编程门阵列电路中的计算地址处加载第二数据模式，第一端口与第二端口断开。 提供用于模拟或数字端口的机制，用于多位数字端口，用于逻辑功能与交叉开关功能的组合，以及用于将数据锁定在交叉开关中。 在一个实施例中，交叉开关是递增地可重新配置的，其中不参与重新配置的端口不受重新配置操作的影响。 描述了对机器视觉系统的应用。

公开(公告)号：US5517619A

公开(公告)日：1996-05-14

申请号：US203265

申请日：1994-02-28

Applicant: Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

Inventor： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

IPC: G06F13/40 ,  G06F15/173 ,  G06F13/38

CPC classification number: G06F15/17375 ,  G06F13/4022 ,  G06F15/17381

Abstract: In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

Abstract translation: 在包括L = n1xn2x - - - xnN处理器元件或以外的设备（以下由处理器元件表示）的并行计算机中，使用Lx（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关的处理器元件的互连网络 总共包括N维网格坐标（i1，i2，...，iN），0

公开(公告)号：US5513369A

公开(公告)日：1996-04-30

申请号：US740542

申请日：1991-08-05

Applicant: Chiman R. Patel ,  Henry Y. Hsu

Inventor： Chiman R. Patel ,  Henry Y. Hsu

IPC: G06F15/173 ,  G06F13/00

CPC classification number: G06F15/17375

Abstract: A star coupler device for interconnecting processors within a data processing system. The star coupler device includes first and second level star couplers. The first level star coupler includes a plurality of inputs and corresponding outputs and functions to logically OR together all signals received at its inputs to generate a first output signal. The second level star coupler also includes a plurality of inputs and corresponding outputs, one of the inputs to the second level star coupler being connected to receive the first output signal. The second level star coupler functions to logically OR together all signals received at its inputs, including the first output signal, to generate a second output signal which is provided at each of its outputs. A switch or multiplexer directs either the first or second output signal to each one of the outputs of the first level star coupler.

Abstract translation: 用于在数据处理系统内互连处理器的星形耦合器装置。 星形耦合器装置包括第一和第二级星形耦合器。 第一级星形耦合器包括多个输入和相应的输出和功能，以将在其输入处接收的所有信号逻辑或或并置以产生第一输出信号。 第二级星形耦合器还包括多个输入和对应的输出，其中一个输入到第二级星形耦合器被连接以接收第一输出信号。 第二级星形耦合器用于将包括第一输出信号的在其输入处接收到的所有信号进行逻辑或或运算，以产生在其每个输出端处提供的第二输出信号。 开关或多路复用器将第一或第二输出信号引导到第一级星形耦合器的每个输出端。

公开(公告)号：US5471592A

公开(公告)日：1995-11-28

申请号：US263504

申请日：1994-06-21

Applicant: Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

Inventor： Robert J. Gove ,  Karl M. Guttag ,  Keith Balmer ,  Nicholas K. Ing-Simmons

IPC: G06F15/167 ,  G06F12/02 ,  G06F12/06 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC classification number: G06F15/17375 ,  G06F12/0284

Abstract: There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.

Abstract translation: 公开了一种在一个实施例中将图像和图形处理器设置为多处理器系统和方法。 该处理器由多个单独的处理器构成，所有处理器都具有到几个存储器的通信链路，而不受限制。 交叉开关用于建立处理器存储器链路，并且整个图像处理器（包括各个处理器，交叉开关和存储器）都包含在单个硅芯片上。

公开(公告)号：US5442772A

公开(公告)日：1995-08-15

申请号：US993142

申请日：1992-12-18

Applicant: Philip L. Childs ,  Nimish S. Radia ,  Joseph F. Skovira

Inventor： Philip L. Childs ,  Nimish S. Radia ,  Joseph F. Skovira

IPC: G06F11/26 ,  G06F13/40 ,  G06F15/173 ,  G06F17/50 ,  H04L1/00 ,  H04L7/033 ,  H04L12/18 ,  H04L12/56 ,  H04Q11/00 ,  H04Q11/04 ,  G06F15/16

CPC classification number: G06F13/4022 ,  G06F15/17375 ,  G06F15/17393 ,  G06F17/5022 ,  H04L1/0057 ,  H04L49/254 ,  H04L7/0338 ,  H04Q11/0478 ,  G06F11/261 ,  H04L49/101 ,  H04L49/201 ,  H04L49/30 ,  H04L49/40 ,  H04Q11/0066

Abstract: A logic simulator is distributed over a plurality of processing nodes for simulating a circuit. A plurality of logic simulation programs execute on respective ones of the nodes, and simulate respective parts of the circuit. Each of the logic simulation programs executes at its own pace, and either receives an input from or supplies an output to another of the nodes. Each of the logic simulation programs also predicts an input when unavailable from another of the nodes. A host broadcasts a breakpoint time to all of the nodes. A plurality of logic simulation controllers execute on respective ones of the nodes, and direct storage of nets and/or states of the logic simulation programs. Each of the logic simulation controllers receives the breakpoint time from the host and reports to the host when the respective logic simulation program has advanced to or past the breakpoint time. When all of the nodes have reported that their respective logic simulation programs have advanced to or past the breakpoint time, this means that nets and states at the breakpoint time are valid. Then, the host obtains from one or more of the nodes values of one or more nets and/or states at the breakpoint time. In another mode of operation, before broadcasting the breakpoint time, the host sends to one of the nodes responsible for generating a condition or event a request to notify the host when the condition or event occurs and a local virtual time that the condition or event occurred. The host then broadcasts the local virtual time as the breakpoint time.

Abstract translation: 逻辑仿真器分布在多个处理节点上用于模拟电路。 多个逻辑仿真程序在相应的节点上执行，并且模拟电路的各个部分。 每个逻辑仿真程序以其自身的速度执行，并且从其中接收输入或将输出提供给另一节点。 每个逻辑仿真程序还预测当从另一个节点不可用时的输入。 主机向所有节点广播断点时间。 多个逻辑模拟控制器在相应的节点上执行，并且直接存储网络和/或逻辑模拟程序的状态。 每个逻辑模拟控制器从主机接收断点时间，并在相应的逻辑模拟程序提前到或超过断点时间时向主机报告。 当所有节点都报告其各自的逻辑仿真程序已经提前到或超过断点时间时，这意味着在断点时间的网络和状态是有效的。 然后，主机从断点处的一个或多个网络和/或状态的一个或多个节点获得值。 在另一种操作模式中，在广播断点时间之前，主机向负责生成条件或事件的节点之一发送在条件或事件发生时通知主机的请求以及发生条件或事件的本地虚拟时间 。 然后，主机将本地虚拟时间广播为断点时间。

公开(公告)号：US5410649A

公开(公告)日：1995-04-25

申请号：US911562

申请日：1992-06-29

Applicant: Robert J. Gove

Inventor： Robert J. Gove

IPC: G06F15/173 ,  G06F15/80 ,  G06F15/00

CPC classification number: G06F15/17375 ,  G06F15/8007

Abstract: A multi-processing system which handles image processing and graphics by constructing a crossbar switch capable of inter-connecting any processor with any memory in any configuration for the interchange of data. The system is capable of connecting n parallel processors to m memories where m is greater than n.

Abstract translation: 一种多处理系统，其通过构建能够将任何处理器与用于数据交换的任何配置中的任何存储器相互连接的交叉开关来处理图像处理和图形。 该系统能够将n个并行处理器连接到m大于n的m个存储器中。

公开(公告)号：US5404537A

公开(公告)日：1995-04-04

申请号：US946986

申请日：1992-09-17

Applicant: Howard T. Olnowich ,  David B. Kirk

Inventor： Howard T. Olnowich ,  David B. Kirk

IPC: G06F15/173 ,  G06F9/46 ,  G06F15/16

CPC classification number: G06F15/17375

Abstract: A method and apparatus for implementing intelligent priority functions at individual switching apparatus devices which comprise switching networks. The intelligent switching functions are capable of operating in real time systems with high efficiency. The switching apparatus has the capability at each stage of the network to make and/or break connections on a priority basis. If a connection is requested at a switch stage and the connection is being used by a lower priority device, the low priority connection is interrupted (broken) and the requested higher priority connection is established. After the high priority connection has completed its usage of the connection, the high priority connection is broken and the lower priority connection is re-established.

Abstract translation: 一种用于在包括交换网络的各个交换设备设备处实现智能优先级功能的方法和装置。 智能切换功能能够以高效率在实时系统中运行。 交换设备在网络的每个阶段具有在优先级上进行和/或断开连接的能力。 如果在交换阶段请求了连接，并且较低优先级的设备正在使用该连接，则低优先级连接将被中断（断开），并建立所请求的较高优先级连接。 高优先级连接完成连接使用后，高优先级连接断开，优先级较低的连接重新建立。

公开(公告)号：US5331315A

公开(公告)日：1994-07-19

申请号：US898081

申请日：1992-06-12

Applicant: Dario B. Crosette

Inventor： Dario B. Crosette

IPC: G06F15/173 ,  H04Q3/54 ,  G06F13/362 ,  H04J3/16 ,  H04Q11/06

CPC classification number: G06F15/17375 ,  G06F15/17343

Abstract: A communication switch apparatus and a method for use in a geographically extensive serial, parallel or hybrid communication network linking a multi-processor or parallel processing system has a very low software processing overhead in order to accommodate random burst of high density data. Associated with each processor is a communication switch. A data source and a data destination, a sensor suite or robot for example, may also be associated with a switch. The configuration of the switches in the network are coordinated through a master processor node and depends on the operational phase of the multi-processor network: data acquisition, data processing, and data exchange. The master processor node passes information on the state to be assumed by each switch to the processor node associated with the switch. The processor node then operates a series of multi-state switches internal to each communication switch. The communication switch does not parse and interpret communication protocol and message routing information. During a data acquisition phase, the communication switch couples sensors producing data to the processor node associated with the switch, to a downlink destination on the communications network, or to both. It also may couple an uplink data source to its processor node. During the data exchange phase, the switch couples its processor node or an uplink data source to a downlink destination (which may include a processor node or a robot), or couples an uplink source to its processor node and its processor node to a downlink destination.

Abstract translation: 在多处理器或并行处理系统的地理上广泛的串行，并行或混合通信网络中使用的通信交换装置和方法具有非常低的软件处理开销以便适应高密度数据的随机突发。 与每个处理器相关联的是一个通讯开关。 例如，数据源和数据目的地，传感器套件或机器人也可以与开关相关联。 网络中的交换机的配置通过主处理器节点协调，并且取决于多处理器网络的操作阶段：数据采集，数据处理和数据交换。 主处理器节点将关于每个交换机假设的状态的信息传递给与交换机相关联的处理器节点。 然后，处理器节点在每个通信交换机内部操作一系列多状态交换机。 通信交换机不解析和解释通信协议和消息路由信息。 在数据采集阶段期间，通信交换机将产生数据的传感器与与交换机相关联的处理器节点耦合到通信网络上的下行链路目的地，或耦合到两者。 它也可以将上行链路数据源耦合到其处理器节点。 在数据交换阶段期间，交换机将其处理器节点或上行链路数据源耦合到下行链路目的地（其可以包括处理器节点或机器人），或将上行链路源耦合到其处理器节点及其处理器节点到下行链路目的地 。