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    DATA RECOVERY MANAGEMENT FOR MEMORY
    62.
    发明公开
    DATA RECOVERY MANAGEMENT FOR MEMORY 审中-公开

    公开(公告)号：US20230153215A1

    公开(公告)日：2023-05-18

    申请号：US17046279

    申请日：2019-10-25

    Applicant: MIcron Technology, Inc.

    Inventor： Minjian Wu

    IPC: G06F11/20 ,  G06F3/06

    CPC classification number: G06F11/2017 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F2201/805

    Abstract: A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.

    STORAGE SYSTEM AND STORAGE CONTROL METHOD
    64.
    发明申请
    STORAGE SYSTEM AND STORAGE CONTROL METHOD 审中-公开

    公开(公告)号：US20190205226A1

    公开(公告)日：2019-07-04

    申请号：US16330333

    申请日：2017-03-24

    Applicant: HITACHI, LTD.

    Inventor： Naoya OKAMURA ,  Masanori FUJII ,  Naoki MORITOKI

    IPC: G06F11/20 ,  G06F3/06

    CPC classification number: G06F11/201 ,  G06F3/0617 ,  G06F3/0635 ,  G06F3/0689 ,  G06F11/2017

    Abstract: Provided are a storage system and a storage control method wherein, when communication is disabled (communication via a data communication path is disabled) in spite of replacement of a second CTL among a first CTL and the second CTL that are redundant storage controllers and that are coupled via the data communication path, the first CTL executes a write process of writing dirty data and data management information to one or more storage devices while maintaining acceptance of I/O requests from a host. The replaced second CTL reads the data management information from the one or more storage devices. The first CTL stops accepting I/O requests from the host. The replaced second CTL starts accepting I/O requests from the host.

    SEMICONDUCTOR DEVICE
    65.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180267729A1

    公开(公告)日：2018-09-20

    申请号：US15977291

    申请日：2018-05-11

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshikazu SATO ,  Haruhiko MATSUMI

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/28 ,  G06F11/20 ,  G06F11/10 ,  G06F11/16

    CPC classification number: G06F3/0631 ,  G06F3/0607 ,  G06F11/1048 ,  G06F11/1052 ,  G06F11/1666 ,  G06F11/2017 ,  G06F13/28 ,  G06F13/4221

    Abstract: A semiconductor device in which unwanted change in the secondary data which must be reliable is suppressed and the need for a considerable increase in the capacity of a memory unit can be avoided. Also it ensures efficient data processing by asymmetric access to the memory unit. It includes a memory unit having a first memory without an error correcting function, a second memory with an error correcting function, and a plurality of access nodes for the memories. A plurality of buses is coupled to the access nodes and a plurality of data processing modules can asymmetrically access the memory unit through the buses. The first memory stores primary data before data processing by the data processing modules, and the second memory stores secondary data after data processing by the data processing modules.

    System and Method for Data Restore Flexibility on Dual Channel NVDIMMs
    66.
    发明申请
    System and Method for Data Restore Flexibility on Dual Channel NVDIMMs 审中-公开

    公开(公告)号：US20180246790A1

    公开(公告)日：2018-08-30

    申请号：US15443530

    申请日：2017-02-27

    Applicant: DELL PRODUCTS, LP

    Inventor： Vadhiraj Sankaranarayanan ,  Bhyrav M. Mutnury ,  Stuart Allen Berke

    IPC: G06F11/20 ,  G06F3/06

    CPC classification number: G06F11/201 ,  G06F3/0619 ,  G06F3/0635 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/2017

    Abstract: A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.

    Chunk redundancy architecture for memory
    68.
    发明授权
    Chunk redundancy architecture for memory 有权

    公开(公告)号：US09996438B2

    公开(公告)日：2018-06-12

    申请号：US15638042

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Toru Tanzawa

    IPC: G06F11/20

    CPC classification number: G06F11/2094 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2017 ,  G06F2201/805 ,  G06F2201/82 ,  G11C29/82

    Abstract: An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.

    CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY
    70.
    发明申请
    CHUNK REDUNDANCY ARCHITECTURE FOR MEMORY 有权

    公开(公告)号：US20170300395A1

    公开(公告)日：2017-10-19

    申请号：US15638042

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Toru TANZAWA

    IPC: G06F11/20

    CPC classification number: G06F11/2094 ,  G06F3/0689 ,  G06F11/1076 ,  G06F11/2017 ,  G06F2201/805 ,  G06F2201/82 ,  G11C29/82

    Abstract: An integrated circuit (IC) includes addressable blocks of memory, and at least one redundant block of memory. A block of memory includes two or more chunks of memory. The IC also includes redundancy control cells. Control circuitry is included to access a first chunk of a redundant block of memory in place of a first remapped chunk one of the addressable blocks of memory, and a second chunk of a redundant block of memory in place of a second remapped chunk one of the addressable blocks of memory, based on the redundancy control cells.

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