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公开(公告)号：US06864900B2
公开(公告)日：2005-03-08
申请号：US09861467
申请日：2001-05-18
CPC分类号： G09G5/363 , G06F3/1431 , G09G5/346
摘要： A graphics system and method for panning from one portion of a stored image to another portion of the image includes a frame buffer, one or more display devices, one or more raster parameter registers, and one or more raster parameter updaters. The image is stored in the frame buffer and each display device is configured to display less than the entire image. A panning operation is initiated by requesting an update of one or more of the raster parameter registers during a next blanking period.
摘要翻译： 用于从存储的图像的一部分平移到图像的另一部分的图形系统和方法包括帧缓冲器，一个或多个显示设备，一个或多个光栅参数寄存器以及一个或多个光栅参数更新器。 图像被存储在帧缓冲器中，并且每个显示设备被配置为显示小于整个图像。 通过在下一个消隐期间请求更新一个或多个光栅参数寄存器来启动平移操作。
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62.发明授权Graphics data synchronization with multiple data paths in a graphics accelerator 有权图形数据同步与图形加速器中的多个数据路径公开(公告)号：US06864892B2
公开(公告)日：2005-03-08
申请号：US10093835
申请日：2002-03-08
CPC分类号： G09G5/36 , G06T15/005
摘要： A system and method for preserving the order of data items through a divergence-and-reconvergence of two or more paths in a hardware device. A host processor may write a first token to a first path in the hardware device. A convergence unit in the hardware device may receive and store the first token in a synchronization register. The host processor may poll the synchronization register to determine when the first token arrives in the synchronization register. In response to determining that the first token has arrived in the synchronization register, the host processor may safely write a sequence of one or more data items to a second path in the hardware device.
摘要翻译： 一种用于通过硬件设备中两个或多个路径的发散和再聚合来保持数据项的顺序的系统和方法。 主处理器可以将第一令牌写入硬件设备中的第一路径。 硬件设备中的会聚单元可以将第一令牌接收并存储在同步寄存器中。 主处理器可以轮询同步寄存器以确定第一个令牌何时到达同步寄存器。 响应于确定第一令牌已经到达同步寄存器，主处理器可以安全地将一个或多个数据项的序列写入硬件设备中的第二路径。
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63.发明授权System and method for performing scale and bias operations by preclamping input image data 有权通过预压缩输入图像数据进行缩放和偏移操作的系统和方法公开(公告)号：US06847378B2
公开(公告)日：2005-01-25
申请号：US10093364
申请日：2002-03-07
CPC分类号： G06T3/4007 , G09G5/363
摘要： In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.
摘要翻译： 在一个实施例中，用于图形系统的比例尺和偏置单元包括预压缩单元，其被配置为接收输入并且如果输入在第一输入范围内则响应地产生等于第一值的输出值。 缩放和偏置单元还包括耦合到预压单元并被配置为对输入执行计算以产生输出值的处理单元。 如果输入在第一输入范围内，则处理单元不执行计算。
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公开(公告)号：US06833834B2
公开(公告)日：2004-12-21
申请号：US10021096
申请日：2001-12-12
IPC分类号： G06F1300
CPC分类号： G09G3/006 , G06F3/1431 , G09G5/001 , G09G5/18 , G09G5/363 , G09G5/395 , G09G2360/123
摘要： A graphics system includes a frame buffer, a write address generator, and a pixel buffer. A burst of pixels received from the frame buffer may not be in display order. In one embodiment, a write address generator calculates a write address for each pixel in the burst of pixels output from the frame buffer. The write address corresponds to a relative display order within the burst for each respective pixel. Each pixel in the burst is stored to its write address in the pixel buffer. This way, the pixels in the burst are stored in display order within the pixel buffer.
摘要翻译： 图形系统包括帧缓冲器，写地址生成器和像素缓冲器。 从帧缓冲器接收到的像素突发可能不是显示顺序。 在一个实施例中，写地址生成器计算从帧缓冲器输出的像素突发中的每个像素的写入地址。 写入地址对应于每个相应像素的突发内的相对显示顺序。 突发中的每个像素被存储到像素缓冲器中的其写入地址。 这样，突发中的像素以像素缓冲器内的显示顺序存储。
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公开(公告)号：US06816161B2
公开(公告)日：2004-11-09
申请号：US10060969
申请日：2002-01-30
IPC分类号： G06F1300
CPC分类号： G06T15/005
摘要： A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.
摘要翻译： 公开了用于处理几何压缩的三维图形数据的图形系统和方法。 在对每个顶点进行变换和点亮之后，使用连通性信息解压缩顶点数据流，并将顶点重新组合成几何图元。 连接信息可以包括网格缓冲器引用，顶点标签或其他类型的信息。 独立缓冲区，队列和/或高速缓存用于同时存储：（a）下一个原语的顶点数据，（b）将被重用的顶点数据，（c）顶点标签，（d）控制标签，（e ）顶点数据被组装成原始图形，（f）准备启动的组合原始图形。 在投入时间以将原始图像处理成像素数据进行显示之前，组合的原始图像可以在定义的视口中进行剪辑测试。 独立缓冲器，队列和/或高速缓存也可以使顶点处理步骤以并行且不同的速率执行。
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公开(公告)号：US06812928B2
公开(公告)日：2004-11-02
申请号：US10060978
申请日：2002-01-30
IPC分类号： G09G539
CPC分类号： G09G5/39 , G06T1/60 , G06T15/04 , G09G2320/0285 , G09G2360/122 , G09G2360/128
摘要： An optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit utilizes knowledge of the repetitive and predictable nature of texture buffer accesses to potentially reduce the number of memory fetches. The unit maintains a queue of pending requests for tiles of data from the memory, and predicts the retrieval of redundant data within short sequences of requests. The redundant data is retrieved from the memory once, and repeated as necessary from local temporary storage registers.
摘要翻译： 描述了一种用于交错存储器并适用于计算机图形系统的优化单元。 该单元利用纹理缓冲器访问的重复性和可预测性质的知识来潜在地减少存储器提取的数量。 该单元维护来自存储器的数据块的待处理请求队列，并且预测在短序列请求内检索冗余数据。 冗余数据从存储器中检索一次，并根据需要从本地临时存储寄存器重复。
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67.发明授权System and method for handling display device requests for display data from a frame buffer 有权用于处理从帧缓冲器显示数据的显示设备请求的系统和方法公开(公告)号：US06806883B2
公开(公告)日：2004-10-19
申请号：US10094930
申请日：2002-03-11
申请人： Michael G. Lavelle , Yan Yan Tang
发明人： Michael G. Lavelle , Yan Yan Tang
IPC分类号： G06F1318
摘要： A graphics system may include a frame buffer, a processing device coupled to access data in the frame buffer, a frame buffer interface coupled to the frame buffer, and an output controller configured to assert a request for display data to provide to a display device. The frame buffer interface may receive the request for display data from the output controller and delay providing the request for display data to the frame buffer if the processing device is currently requesting access to a portion of the frame buffer targeted by the request for display data. For example, if the frame buffer includes several memory banks and the request for display data targets a first bank, the frame buffer interface may delay providing the request for display data to the frame buffer if the processing device is currently requesting access to the first bank.
摘要翻译： 图形系统可以包括帧缓冲器，耦合到访问帧缓冲器中的数据的处理设备，耦合到帧缓冲器的帧缓冲器接口，以及输出控制器，被配置为断言显示数据的请求以提供给显示设备。 帧缓冲器接口可以从输出控制器接收对显示数据的请求，并且如果处理设备正在请求访问由显示数据请求所针对的帧缓冲区的一部分，则向帧缓冲器提供对显示数据的请求的延迟。 例如，如果帧缓冲器包括多个存储体并且显示数据的请求针对第一存储体，则如果处理设备正在请求访问第一存储体，则帧缓冲器接口可以延迟向帧缓冲器提供对显示数据的请求 。
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公开(公告)号：US06784881B2
公开(公告)日：2004-08-31
申请号：US10037410
申请日：2002-01-04
申请人： Michael A. Wasserman , Michael G. Lavelle , Justin Michael Mahan , David Naegle , Glenn J. Gracon
发明人： Michael A. Wasserman , Michael G. Lavelle , Justin Michael Mahan , David Naegle , Glenn J. Gracon
IPC分类号： G09G500
CPC分类号： G06F3/1431 , G09G5/12 , G09G5/363
摘要： A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.
摘要翻译： 被配置为将从属显示通道同步到主显示通道的图形系统可以包括被配置为提供帧事件指示和从属显示定时发生器的主显示定时发生器。 从显示定时发生器可以被配置为接收帧事件指示，并且响应于在其有效显示周期期间接收帧事件指示，从属显示定时发生器可以被配置为等待直到其当前活动显示周期结束然后跳转 到其同步点。 或者，从显示定时发生器可以被配置为立即或在当前水平行的结束之后跳转到其同步点，并且可以在下一活动显示周期期间显示中断帧中的任何剩余显示信息。
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公开(公告)号：US06720969B2
公开(公告)日：2004-04-13
申请号：US09861172
申请日：2001-05-18
IPC分类号： G09G536
CPC分类号： G06F12/0897 , G06T1/60 , G06T15/005 , G09G5/363 , G09G5/39 , G09G2360/121 , G09G2360/122 , Y02D10/13
摘要： An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.
摘要翻译： 描述了一种用于3D-RAM帧缓冲器并适用于计算机图形系统的外部高速缓存管理单元。 该单元可以通过根据存储在脏标签位阵列中的状态信息执行部分块回写来减少3D-RAM内的功耗。 在空的存储器循环期间提供了周期性的一级缓存块清理。
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公开(公告)号：US06661423B2
公开(公告)日：2003-12-09
申请号：US09861184
申请日：2001-05-18
IPC分类号： G06F1206
CPC分类号： G06T1/60
摘要： A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.
摘要翻译： 描述适用于计算机图形系统的存储器阵列管理单元。 该单元特别设计用于方便存储图形数据的瓦片。 提供了瓦片和存储器块边界之间的对准检测，其中未对准导致自动抽取以产生子图块并生成多个存储器写入序列。
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