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    LEAKAGE RESISTANT RRAM/MIM STRUCTURE
    61.
    发明申请
    LEAKAGE RESISTANT RRAM/MIM STRUCTURE 审中-公开

    公开(公告)号：US20170309816A1

    公开(公告)日：2017-10-26

    申请号：US15647579

    申请日：2017-07-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L45/00 ,  H01L49/02

    CPC classification number: H01L45/1253 ,  H01L28/40 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16

    Abstract: A method of manufacturing an integrated circuit device. In the method, a plurality of contacts are formed over a substrate, and one or more bottom electrode layers are formed over the plurality of contacts. A first dielectric layer is formed such that a first base region of the first dielectric layer is in contact with the one or more bottom electrode layers and a second base region of the first dielectric layer is not in contact with the one or more bottom electrode layers. One or more top electrode layers are formed over the first dielectric layer. Patterning is then performed by etching through the one or more top electrode layers and by etching through the first dielectric layer to form a metal-insulator-metal structure. The patterning removes a portion of the second base region, but does not remove the first base region.

    Leakage resistant RRAM/MIM structure
    62.
    发明授权
    Leakage resistant RRAM/MIM structure 有权

    公开(公告)号：US09728719B2

    公开(公告)日：2017-08-08

    申请号：US14261526

    申请日：2014-04-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming Chyi Liu ,  Yuan-Tai Tseng ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC: H01L47/00 ,  H01L45/00 ,  H01L49/02

    CPC classification number: H01L45/1253 ,  H01L28/40 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/16

    Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.

    Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure
    63.
    发明授权
    Split gate flash memory structure with a damage free select gate and a method of making the split gate flash memory structure 有权
    分闸门闪存结构，具有无损选择栅极和分离栅闪存结构的方法

    公开(公告)号：US09502515B2

    公开(公告)日：2016-11-22

    申请号：US14980165

    申请日：2015-12-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC: H01L21/8238 ,  H01L29/792 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

    CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

    Abstract: A method of manufacturing a split gate flash memory cell is provided. A select gate is formed on a semiconductor substrate. A sacrificial spacer is formed laterally adjacent to the select gate and on a first side of the select gate. A charge trapping layer is formed lining upper surfaces of the select gate and the sacrificial spacer, and further lining a sidewall surface of the select gate on a second side of the select gate that is opposite the first side of the select gate. A memory gate is formed over the charge trapping layer and on the second side of the select gate. The sacrificial spacer is removed. The resulting semiconductor structure is also provided.

    Abstract translation: 提供了一种制造分离栅闪存单元的方法。 选择栅极形成在半导体衬底上。 牺牲隔离物横向邻近选择栅极并在选择栅极的第一侧上形成。 在选择栅极和牺牲隔离物的上表面上形成电荷捕获层，并且进一步在选择栅极的与选择栅极的第一侧相对的第二侧上衬里选择栅极的侧壁表面。 存储栅极形成在电荷俘获层上和选择栅极的第二侧上。 去除牺牲隔离物。 还提供所得的半导体结构。

    Split Gate Flash Memory Structure with a Damage Free Select Gate and a Method of Making the Split Gate Flash Memory Structure
    64.
    发明申请
    Split Gate Flash Memory Structure with a Damage Free Select Gate and a Method of Making the Split Gate Flash Memory Structure 有权
    具有无损耗选择门的分流门闪存结构和分离门闪存结构的方法

    公开(公告)号：US20150380568A1

    公开(公告)日：2015-12-31

    申请号：US14316864

    申请日：2014-06-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yuan-Tai Tseng ,  Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC: H01L29/792 ,  H01L29/66

    CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L29/66484 ,  H01L29/66833 ,  H01L29/792

    Abstract: A method of manufacturing a semiconductor structure of a pair of split gate flash memory cells is provided. A pair of select gates spaced on a semiconductor substrate is formed, and a sacrificial spacer filling a central region between the select gates is formed. A charge trapping dielectric layer is formed conformally along sidewalls of the select gates and over top surfaces of the sacrificial spacer and the select gates, and a pair of memory gates corresponding to the pair of select gates is formed over and laterally abutting the charge trapping dielectric layer. The resulting semiconductor structure is also provided.

    Abstract translation: 提供了一对制造分离栅闪存单元的半导体结构的方法。 形成在半导体衬底上间隔开的一对选择栅极，并且形成填充选择栅极之间的中心区域的牺牲隔离物。 电荷捕获电介质层沿着选择栅极的侧壁和牺牲间隔物和选择栅极的顶表面保形地形成，并且对应于该对选择栅极的一对存储栅极形成在电荷捕获电介质上方并横向邻接 层。 还提供所得的半导体结构。

    ASYMMETRIC FORMATION APPROACH FOR A FLOATING GATE OF A SPLIT GATE FLASH MEMORY STRUCTURE
    65.
    发明申请
    ASYMMETRIC FORMATION APPROACH FOR A FLOATING GATE OF A SPLIT GATE FLASH MEMORY STRUCTURE 有权
    分流闸闪存存储结构浮动门的不对称形成方法

    公开(公告)号：US20150372121A1

    公开(公告)日：2015-12-24

    申请号：US14308872

    申请日：2014-06-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

    IPC: H01L29/66 ,  H01L29/49 ,  H01L29/788

    CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

    Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

    Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括具有源极区和漏极区的半导体衬底。 此外，半导体结构包括在源极和漏极区域之间间隔开半导体衬底的浮置栅极，字线和擦除栅极，其中浮置栅极布置在字线和擦除栅极之间。 半导体结构还包括设置在字线和浮置栅极之间的第一电介质侧壁区域以及设置在擦除栅极和浮置栅极之间的第二电介质侧壁区域。 第一电介质侧壁区域的厚度大于第二电介质侧壁区域的厚度。 还提供了制造半导体结构的方法和包括半导体结构的集成电路。

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