-
公开(公告)号：US20170187380A1
公开(公告)日：2017-06-29
申请号：US15458692
申请日：2017-03-14
Applicant: STMicroelectronics S.r.l.
Inventor： Salvatore Marco Rosselli , Daniele Mangano , Riccardo Condorelli
IPC: H03K19/00 , H03K19/173 , G06F15/78 , H03K19/177
CPC classification number: H03K19/0008 , G06F15/7867 , G06F2209/507 , H03K19/1737 , H03K19/1776
Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.
-
公开(公告)号：US20170139461A1
公开(公告)日：2017-05-18
申请号：US14943472
申请日：2015-11-17
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Roberto LAROSA , Daniele Mangano , Riccardo Condorelli , Giulio Zoppi , Natale Aiello
CPC classification number: G06F1/3206 , G06F1/26
Abstract: An electronic device may include a transducer configured to generate an electrical output responsive to an input, and a data storage element configured to change state responsive to the transducer. The electronic device may include a power circuit configured to turn on and supply power responsive to the data storage element changing state, and a processing circuit configured to be powered by the power circuit.
-
63.发明授权公开(公告)号：US09471521B2
公开(公告)日：2016-10-18
申请号：US14278403
申请日：2014-05-15
Applicant: STMicroelectronics S.r.l.
Inventor： Mirko Dondini , Daniele Mangano , Giuseppe Falconeri
IPC: G06F13/28
CPC classification number: G06F13/28
Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。
-
64.发明授权Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer 有权用于排序乱序数据的缓冲器，以及用于管理缓冲器的相应集成电路和方法公开(公告)号：US09093133B2
公开(公告)日：2015-07-28
申请号：US14143383
申请日：2013-12-30
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Salvatore Marco Rosselli , Giuseppe Falconeri
CPC classification number: G11C7/1006 , G06F5/10 , G06F2205/106 , G06F2205/123
Abstract: A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.
Abstract translation: 用于排序无序数据的缓冲器包括具有用于临时存储数据的多个存储器位置的存储器和被配置为当存储器位置包含有效数据时生成控制信号的检测电路。 检测电路包括被配置用于产生识别包含有效数据的存储位置的有效信号的第一块和被配置为根据有效信号确定搜索指针的搜索电路。 在每个存储器位置包含有效数据的情况下，搜索指针指示最后的存储器位置。 在至少一个存储器位置仍然空闲的情况下，搜索指针指示第一存储器位置是空闲的。
-
公开(公告)号：US20150033821A1
公开(公告)日：2015-02-05
申请号：US14444920
申请日：2014-07-28
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano
IPC: G01C25/00
CPC classification number: G01C25/005 , G01C19/00 , G01C21/10 , G01C21/12 , G01C21/16 , G01C21/18 , G01C25/00 , G01P21/00
Abstract: A method for real-time calibration of a gyroscope, configured for supplying a value of angular velocity that is function of a first angle of rotation about a first angular-sensing axis that includes defining a time interval, acquiring from an accelerometer an equivalent value of angular velocity that can be associated to the first angle of rotation; calculating a deviation between the value of angular velocity and the equivalent value of angular velocity; iteratively repeating the previous steps through the time interval, incrementing or decrementing an offset variable by a first predefined value on the basis of the values assumed by the deviations during the iterations, and updating the value of angular velocity as a function of the offset variable.
Abstract translation: 一种用于陀螺仪的实时校准的方法，其被配置为提供围绕第一角度感测轴线的第一旋转角函数的角速度值，所述第一角度感测轴线包括限定时间间隔，从加速度计获取等效值 可以与第一旋转角度相关联的角速度; 计算角速度值和角速度等效值之间的偏差; 在所述时间间隔内迭代地重复前述步骤，基于由迭代期间的偏差假设的值，将偏移变量递增或递减第一预定义值，以及作为偏移变量的函数更新角速度的值。
-
Patent Agency Ranking
公开(公告)号：US11906995B2
公开(公告)日：2024-02-20
申请号：US17836417
申请日：2022-06-09
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Francesco Clerici , Pasquale Butta'
Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.
-
公开(公告)号：US11803226B2
公开(公告)日：2023-10-31
申请号：US16874020
申请日：2020-05-14
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Michele Alessandro Carrano , Pasquale Butta′ , Sergio Abenda
IPC: G06F1/3234 , H03K3/037 , G06F1/3296
CPC classification number: G06F1/325 , G06F1/3243 , H03K3/037
Abstract: A power-saving system includes a retention memory element for a retained peripheral that is set to a logic state during an operational-power mode and maintains the logic state during an enhanced power-saving mode. The power-saving system also includes a non-retention memory element for a non-retained peripheral that is set to a logic state during the operational-power mode of the power-saving system; and a controller that instructs the retention memory element to maintain its logic state while in an enhanced power-saving mode.
-
公开(公告)号：US11703897B2
公开(公告)日：2023-07-18
申请号：US16810639
申请日：2020-03-05
Inventor： Michel Cuenca , Bruno Gailhard , Daniele Mangano
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.
-
公开(公告)号：US10788870B2
公开(公告)日：2020-09-29
申请号：US16405086
申请日：2019-05-07
Applicant: STMicroelectronics S.r.l.
Inventor： Daniele Mangano , Gaetano Di Stefano , Mirko Dondini
IPC: G06F1/24 , G06F11/267 , H03K3/037
Abstract: A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
-
公开(公告)号：US10451703B2
公开(公告)日：2019-10-22
申请号：US16213534
申请日：2018-12-07
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo Condorelli , Daniele Mangano
Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.
-
-
-
-
-
-
-
-
-
Search Results
75
records
(took 0.037 seconds)
