公开(公告)号：US20110053341A1

公开(公告)日：2011-03-03

申请号：US12941527

申请日：2010-11-08

申请人： Ronald Kakoschke ,  Franz Schuler

发明人： Ronald Kakoschke ,  Franz Schuler

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

摘要翻译： 公开了一种存储器电路装置和制造方法。 存储器电路装置具有存储单元区域。 存储单元区域包含存储单元晶体管，其一列使用三栅极区域选择晶体管来选择。 晶体管具有延伸到隔离沟槽中的栅极区域。 隔离沟槽将存储单元阵列的不同列中的存储单元隔离开。

公开(公告)号：US07291881B2

公开(公告)日：2007-11-06

申请号：US11592844

申请日：2006-11-02

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L29/76

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

公开(公告)号：US07262456B2

公开(公告)日：2007-08-28

申请号：US11273668

申请日：2005-11-14

申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

IPC分类号： H01L27/788 ,  H01L21/366

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

摘要翻译： 本公开涉及位线结构和相关联的位线结构的制造方法。 在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。 隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

公开(公告)号：US20060043420A1

公开(公告)日：2006-03-02

申请号：US10513163

申请日：2004-03-18

申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

IPC分类号： H01L27/10

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。

公开(公告)号：US20050269600A1

公开(公告)日：2005-12-08

申请号：US10529049

申请日：2003-09-19

申请人： Ronald Kakoschke

发明人： Ronald Kakoschke

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76 ,  H01L21/335

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7855 ,  H01L29/78612

摘要： An integrated field-effect transistor is described in which a substrate region is surrounded by: two terminal regions (a source region and a drain region), two electrically insulating insulating layers, two electrically insulating regions, and an electrically conductive connecting region. The insulating layers are arranged at mutually opposite sides of the substrate region and are adjoined by control regions. The insulating regions are arranged at mutually opposite sides of the substrate region. The electrically conductive connecting region produces an electrically conductive connection between one terminal region and the substrate region. The connecting region includes a metal-semiconductor compound. Part of a covering area of the substrate region is covered by the connecting region, which extends further over a covering area of the source reqion. The part of the covering area of the substrate region covers the substrate region between the two insulating layers and between the two control regions.

摘要翻译： 描述了一种集成的场效应晶体管，其中衬底区域被两个端子区域（源极区域和漏极区域），两个电绝缘绝缘层，两个电绝缘区域和导电连接区域包围。 绝缘层布置在基板区域的彼此相对的两侧，并且由控制区域邻接。 绝缘区域布置在基板区域的彼此相对的两侧。 导电连接区域在一个端子区域和衬底区域之间产生导电连接。 连接区域包括金属半导体化合物。 衬底区域的覆盖区域的一部分被连接区域覆盖，该连接区域进一步延伸到源区域的覆盖区域上。 衬底区域的覆盖区域的一部分覆盖两个绝缘层之间和两个控制区域之间的衬底区域。

公开(公告)号：US06909139B2

公开(公告)日：2005-06-21

申请号：US10607610

申请日：2003-06-27

申请人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

发明人： Danny Shum ,  Georg Tempel ,  Ronald Kakoschke

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546

摘要： An integrated circuit has a high voltage area, a logic area and a memory array for forming a system on a chip that includes linear, logic and memory devices. The memory array has floating gate transistors disposed in a triple well structure with a raised drain bit line 13 substantially vertically aligned with a buried source bit line 14. The memory array separates the columns with deep trenches 46 that may also be formed into charge pump capacitors.

摘要翻译： 集成电路具有高电压区域，逻辑区域和用于在包括线性，逻辑和存储器件的芯片上形成系统的存储器阵列。 存储器阵列具有布置在三阱结构中的浮置栅极晶体管，其高位漏极位线13基本上与掩埋源极线14垂直对准。 存储器阵列将列可以形成为电荷泵电容器的深沟槽46分离。

公开(公告)号：US06376875B1

公开(公告)日：2002-04-23

申请号：US09401385

申请日：1999-09-22

申请人： Ronald Kakoschke ,  Holger Sedlak

发明人： Ronald Kakoschke ,  Holger Sedlak

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L29/7883

摘要： A semiconductor component, in particular an EEPROM, and a production method therefor, avoid an avalanche breakdown from a buried channel to a substrate through the use of a special lateral dopant profile in the buried channel, in which a peripheral zone of the buried channel has a higher effective doping than a region located below a tunnel window. The lateral dopant profile is produced through the use of a compensation implantation with dopant atoms of the conduction type opposite that of the buried channel.

摘要翻译： 一种半导体元件，特别是一种EEPROM及其制造方法，通过在掩埋沟道中使用特殊的横向掺杂剂分布来避免从掩埋沟道到衬底的雪崩击穿，其中掩埋沟道的周边区域具有 比位于隧道窗下方的区域更有效的掺杂。 通过使用具有与掩埋沟道的导电类型相反的导电类型的掺杂剂原子的补偿注入来产生横向掺杂剂分布。

公开(公告)号：US08728907B2

公开(公告)日：2014-05-20

申请号：US12941527

申请日：2010-11-08

申请人： Ronald Kakoschke ,  Franz Schuler

发明人： Ronald Kakoschke ,  Franz Schuler

IPC分类号： H01L21/8242

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

摘要： A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

摘要翻译： 公开了一种存储器电路装置和制造方法。 存储器电路装置具有存储单元区域。 存储单元区域包含存储单元晶体管，其一列使用三栅极区域选择晶体管来选择。 晶体管具有延伸到隔离沟槽中的栅极区域。 隔离沟槽隔离存储单元阵列的不同列中的存储单元。

公开(公告)号：US08552475B2

公开(公告)日：2013-10-08

申请号：US13297284

申请日：2011-11-16

申请人： Ronald Kakoschke ,  Klaus Schruefer

发明人： Ronald Kakoschke ,  Klaus Schruefer

IPC分类号： H01L29/80

CPC分类号： H01L27/1052 ,  H01L21/84 ,  H01L27/115 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/41791 ,  H01L29/785 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141

摘要： One or more embodiments relate to a memory device, comprising: a memory element; and a FinFET select device including a fin, a gate line supported by the fin, and a contact element coupled between a surface of the fin and the memory element, the contact element being in direct contact with a top surface of the fin.

摘要翻译： 一个或多个实施例涉及存储器设备，包括：存储器元件; 以及FinFET选择装置，其包括翅片，由所述翅片支撑的栅极线以及耦合在所述鳍片的表面和所述存储元件之间的接触元件，所述接触元件与所述鳍片的顶表面直接接触。

公开(公告)号：US08183120B2

公开(公告)日：2012-05-22

申请号：US12943055

申请日：2010-11-10

申请人： Ronald Kakoschke ,  Klaus Schruefer

发明人： Ronald Kakoschke ,  Klaus Schruefer

IPC分类号： H01L21/331

CPC分类号： H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/785

摘要： One or more embodiments relate to a method, comprising forming an implant on a substrate surface; selectively etching the wafer surface to form an elongated fin including portion of the implant; forming collector/emitter regions adjacent opposing ends of the fin; and forming a base region intermediate the collector/emitter regions.

摘要翻译： 一个或多个实施例涉及一种方法，包括在衬底表面上形成植入物; 选择性地蚀刻晶片表面以形成包括植入物的部分的细长翅片; 形成邻近翅片相对端的收集器/发射极区域; 以及在集电极/发射极区域之间形成基极区域。