公开(公告)号：US08284887B2

公开(公告)日：2012-10-09

申请号：US12656833

申请日：2010-02-17

申请人： Hidekazu Kikuchi ,  Hideo Morohashi ,  Tomokazu Tanaka

发明人： Hidekazu Kikuchi ,  Hideo Morohashi ,  Tomokazu Tanaka

IPC分类号： H03D3/24

CPC分类号： H03L7/091 ,  H03K5/131 ,  H03K2005/00065 ,  H03K2005/00221 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0898 ,  H04L7/033

摘要： Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

摘要翻译： 本文公开了一种时钟数据恢复电路，包括：第一相位检测器; 环路滤波器 电荷泵; 压控振荡器; 第二相位检测器; 相位修正信息生成部; 以及相位校正信息添加部。

公开(公告)号：US08271698B2

公开(公告)日：2012-09-18

申请号：US12970540

申请日：2010-12-16

申请人： Yasuhisa Nakajima ,  Hidekazu Kikuchi

发明人： Yasuhisa Nakajima ,  Hidekazu Kikuchi

IPC分类号： G06F3/00

CPC分类号： H04N21/43615 ,  H04N5/775 ,  H04N7/163 ,  H04N21/234309 ,  H04N21/4122 ,  H04N21/4135 ,  H04N21/43632 ,  H04N21/43635

摘要： The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source 71 performs bidirectional IP communication with an HDMI (R) sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI (R) source 71 or the receiver 82 is selected. The present invention is applicable to, for example, HDMI (R).

摘要翻译： 本发明涉及用于在保持兼容性的同时提供高速双向通信的通信系统，发射机，接收机，通信方法，程序和通信电缆。 当HDMI（R）源71使用CEC线84和信号线141与HDMI（R）接收器72进行双向IP通信时，切换控制单元121控制开关133，使得当数据被发送时，开关 133选择形成从转换单元131输出的差分信号的构成信号，并且当发送数据时，开关133选择形成从接收器82输出的差分信号的构成信号。当仅使用CEC线84执行双向通信时 切换控制单元121控制开关133，使得从HDMI（R）源71或接收器82输出的CEC信号被选择。 本发明可应用于例如HDMI（R）。

公开(公告)号：US20110304399A1

公开(公告)日：2011-12-15

申请号：US13067935

申请日：2011-07-08

申请人： Hidekazu Kikuchi ,  Tomokazu Tanaka ,  Kunio Gosho

发明人： Hidekazu Kikuchi ,  Tomokazu Tanaka ,  Kunio Gosho

IPC分类号： H03F1/00 ,  H03F3/04

CPC分类号： H04L25/0282

摘要： Disclosed herein is a driver amplifier circuit, including: a first current source transistor of a first conductivity type, and a second current source transistor of the first conductivity type, control voltages being supplied to gates of the first current source transistor and the second current source transistor, respectively; a first switching transistor of the first conductivity type, and a second switching transistor of the first conductivity type; a third switching transistor of a second conductivity type, and a fourth switching transistor of the second conductivity type; first, second, third, and fourth resistor elements; and a first output node and a second output node.

摘要翻译： 这里公开了一种驱动放大器电路，包括：第一导电类型的第一电流源晶体管和第一导电类型的第二电流源晶体管，控制电压被提供给第一电流源晶体管和第二电流源的栅极 晶体管; 第一导电类型的第一开关晶体管和第一导电类型的第二开关晶体管; 第二导电类型的第三开关晶体管和第二导电类型的第四开关晶体管; 第一，第二，第三和第四电阻器元件; 以及第一输出节点和第二输出节点。

公开(公告)号：US07982538B2

公开(公告)日：2011-07-19

申请号：US12617262

申请日：2009-11-12

申请人： Hidekazu Kikuchi ,  Gen Ichimura ,  Yukihisa Kinugasa

发明人： Hidekazu Kikuchi ,  Gen Ichimura ,  Yukihisa Kinugasa

IPC分类号： H03F3/45

CPC分类号： H03F3/45273 ,  G05F3/262

摘要： A differential includes first and second current mirror circuits that provide the gates of slave transistors with gate voltages of master transistors via a voltage follower where a slew rate at a rise time is equal to a slew rate at a fall time. Thus, when the master current is increased or decreased, an incremental change in slave current and a decremental change in slave current are symmetrical with each other. The use of such current mirrors in a differential manner leads to no generation of common mode noise even in these changes.

摘要翻译： 差分器包括第一和第二电流镜电路，其通过电压跟随器提供从晶体管的栅极与主晶体管的栅极电压，其中上升时间的转换速率等于在下降时间的转换速率。 因此，当主电流增加或减小时，从电流的增量变化和从电流的递减变化彼此对称。 以这种差分方式使用这种电流镜子即使在这些变化中也不会产生共模噪声。

公开(公告)号：US07936401B2

公开(公告)日：2011-05-03

申请号：US12312428

申请日：2007-11-07

申请人： Yasuhisa Nakajima ,  Hidekazu Kikuchi

发明人： Yasuhisa Nakajima ,  Hidekazu Kikuchi

IPC分类号： H04N5/38 ,  H04N5/44

CPC分类号： H04N21/43615 ,  H04N5/775 ,  H04N7/163 ,  H04N21/234309 ,  H04N21/4122 ,  H04N21/4135 ,  H04N21/43632 ,  H04N21/43635

摘要： The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source 71 performs bidirectional IP communication with an HDMI (R) sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI (R) source 71 or the receiver 82 is selected. The present invention is applicable to, for example, HDMI (R).

摘要翻译： 本发明涉及用于在保持兼容性的同时提供高速双向通信的通信系统，发射机，接收机，通信方法，程序和通信电缆。 当HDMI（R）源71使用CEC线84和信号线141与HDMI（R）接收器72进行双向IP通信时，切换控制单元121控制开关133，使得当数据被发送时，开关 133选择形成从转换单元131输出的差分信号的构成信号，并且当发送数据时，开关133选择形成从接收器82输出的差分信号的构成信号。当仅使用CEC线84执行双向通信时 切换控制单元121控制开关133，使得从HDMI（R）源71或接收器82输出的CEC信号被选择。 本发明可应用于例如HDMI（R）。

公开(公告)号：US20100290541A1

公开(公告)日：2010-11-18

申请号：US12844447

申请日：2010-07-27

申请人： Gen Ichimura ,  Hidekazu Kikuchi ,  Yasuhisa Nakajima

发明人： Gen Ichimura ,  Hidekazu Kikuchi ,  Yasuhisa Nakajima

IPC分类号： H04B3/00

CPC分类号： H04L25/0276 ,  H04J3/0638 ,  H04J3/0641 ,  H04L7/0016 ,  H04L7/0091 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/493 ,  H04N21/43615 ,  H04N21/43635 ,  H04N21/64322

摘要： A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

公开(公告)号：US07822143B2

公开(公告)日：2010-10-26

申请号：US10981288

申请日：2004-11-04

申请人： Hidekazu Kikuchi

发明人： Hidekazu Kikuchi

IPC分类号： H04L25/49 ,  H04B1/38

CPC分类号： H04L25/4917 ,  H03M5/20 ,  H03M9/00 ,  H04L7/033

摘要： The present invention provides a data transfer system including a data transmitter and a data receiver. The data transmitter converts a plurality of bits of transmission parallel data into serial data and generates a multi-level logic signal representing a plurality of bits of information in one symbol, the information being obtained by combining the serial data with a word clock as one-bit information. The word clock indicates a word delimiter in the serial data. The data receiver receives the transmitted multi-level logic signal, extracts the serial data and the word clock from the signal, and reproduces the parallel data based on the extracted word clock. In the data transfer system, a multi-bit digital signal can be transmitted as one signal including a word clock. Thus, components and mounting space to be allocated to transfer can be reduced.

摘要翻译： 本发明提供一种包括数据发送器和数据接收器的数据传输系统。 数据发送器将多个传输并行数据位转换为串行数据，并产生表示一个符号中的多个位的信息的多电平逻辑信号，该信息是通过将串行数据与字时钟组合而获得的， 位信息。 字时钟表示串行数据中的字分隔符。 数据接收器接收发送的多电平逻辑信号，从信号中提取串行数据和字时钟，并根据提取的字时钟重现并行数据。 在数据传送系统中，多位数字信号可以作为包括字时钟的一个信号发送。 因此，可以减少要分配用于传送的部件和安装空间。

公开(公告)号：US20080284504A1

公开(公告)日：2008-11-20

申请号：US12140351

申请日：2008-06-17

申请人： Makoto Hirota ,  Hidekazu Kikuchi ,  Sampei Miyamoto

发明人： Makoto Hirota ,  Hidekazu Kikuchi ,  Sampei Miyamoto

IPC分类号： G05F3/16

CPC分类号： H03K19/0016

摘要： This device has a first circuit including a first field effect transistor and a second circuit coupled to a source of the first electric field transistor. The second circuit applies a first source bias voltage, which does not reversely bias between a source and a body of the first field effect transistor, to the first field effect transistor during the operation mode of the first circuit, and applies a second source bias voltage, which reversely biases between the source and the body of the first field effect transistor, to the first field effect transistor during the standby mode of the first circuit. During the standby mode of the first circuit, the leakage current that flows through the first FET is reduced by means of the reverse bias effect produced by applying the second source bias voltage to the source of the first FET.

摘要翻译： 该器件具有包括耦合到第一电场晶体管的源极的第一场效应晶体管和第二电路的第一电路。 第二电路在第一电路的操作模式期间施加第一源极偏置电压，其不在第一场效应晶体管的源极和本体之间反向偏置到第一场效应晶体管，并施加第二源极偏置电压 ，其在第一电路的待机模式期间将第一场效应晶体管的源极和主体之间的偏置反向偏移到第一场效应晶体管。 在第一电路的待机模式期间，通过将第二源偏置电压施加到第一FET的源而产生的反向偏置效应，流过第一FET的漏电流减小。

公开(公告)号：US20080070379A1

公开(公告)日：2008-03-20

申请号：US11850833

申请日：2007-09-06

申请人： Hidekazu Kikuchi

发明人： Hidekazu Kikuchi

IPC分类号： H01L21/00

CPC分类号： H01L21/76898 ,  H01L21/78

摘要： The present invention provides a method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for dividing the plurality of device regions, and a lower surface (second surface) opposite from the upper surface (first surface), forming upper layer wires on the device regions of the upper surface (first surface), etching the semiconductor wafer from a side of the lower surface (second surface) to form a through hole through which the upper layer wire is exposed, and to form a groove in a region of the lower surface (second surface) corresponding to the partition region of the upper surface (first surface), and dicing the semiconductor wafer to form individual device regions.

摘要翻译： 本发明提供了一种制造半导体器件的方法，该半导体器件能够在切割时防止切割部分变得切屑。 制造半导体器件的方法包括制备具有包括多个器件区域的上表面（第一表面）和用于分割多个器件区域的分隔区域的半导体晶片和与上表面相对的下表面（第二表面） （第一表面），在上表面（第一表面）的器件区域上形成上层布线，从下表面（第二表面）侧蚀刻半导体晶片，形成上层布线露出的通孔 并且在与上表面（第一表面）的分隔区域对应的下表面（第二表面）的区域中形成凹槽，并且切割半导体晶片以形成单独的器件区域。

公开(公告)号：US20050182744A1

公开(公告)日：2005-08-18

申请号：US10879182

申请日：2004-06-30

申请人： Isami Kawabata ,  Hidekazu Kikuchi ,  Ryutaro Asari ,  Motoyuki Osugi ,  Sunao Tomita

发明人： Isami Kawabata ,  Hidekazu Kikuchi ,  Ryutaro Asari ,  Motoyuki Osugi ,  Sunao Tomita

IPC分类号： G06F9/44 ,  G06F7/00

CPC分类号： G06F8/36 ,  Y10S707/99956

摘要： An information processing system which constructs a program by combining a plurality of functional units, has an information table for management of components, etc. each of which is a functional unit of a program, and the information table stores plural pieces of management information for individual management of the use record of each component so that the information can be referred to as the reference of reliability when the component is reused, and the management information can be sequentially updated based on the actual use record.

摘要翻译： 通过组合多个功能单元构建程序的信息处理系统具有作为程序的功能单元的组件管理信息表等，并且信息表存储用于个体的多个管理信息 管理每个组件的使用记录，使得可以将该信息称为重新使用组件时的可靠性的参考，并且可以基于实际使用记录顺序地更新管理信息。