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    Compensated triple gate driving circuit, a method, and a display apparatus
    61.
    发明授权
    Compensated triple gate driving circuit, a method, and a display apparatus 有权

    公开(公告)号：US11217150B2

    公开(公告)日：2022-01-04

    申请号：US16485994

    申请日：2018-09-06

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

    IPC: G09G3/36 ,  G11C19/28 ,  G09G3/32

    Abstract: The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.

    A PIXEL ARRAY SUBSTRATE, A DRIVING METHOD, AND A DISPLAY APPARATUS
    62.
    发明申请
    A PIXEL ARRAY SUBSTRATE, A DRIVING METHOD, AND A DISPLAY APPARATUS 有权

    公开(公告)号：US20210356785A1

    公开(公告)日：2021-11-18

    申请号：US16344023

    申请日：2018-09-30

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Lijun Yuan ,  Mingfu Han ,  Haoliang Zheng ,  Guangliang Shang ,  Xing Yao ,  Shunhang Zhang

    IPC: G02F1/1368 ,  G02F1/133

    Abstract: The present application discloses a pixel array substrate. The pixel array substrate includes a plurality of pixels arranged in an array having multiple data-input terminals. N columns of subpixels per each column of pixels are associated with N sets of M numbers of data lines. N is an integer equal to and greater than 1 and M is an even number equal to or greater than 2. The pixel array substrate also includes N sets of M numbers of switches coupled respectively to the N sets of M numbers of data lines. Control terminals of each set of M numbers of switches are respectively coupled to M numbers of clock-signal terminals to receive respective clock control signals to control M groups of subpixels in each corresponding one column of subpixels for connecting with one of the multiple data-input terminals respectively via each corresponding set of M numbers of data lines.

    Pixel driving circuit and method for driving the same, pixel unit and display panel
    66.
    发明授权
    Pixel driving circuit and method for driving the same, pixel unit and display panel 有权

    公开(公告)号：US10818239B2

    公开(公告)日：2020-10-27

    申请号：US16399612

    申请日：2019-04-30

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Lijun Yuan ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han

    IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  H01L27/32

    Abstract: The present disclosure provides a pixel driving circuit and a method for driving the same, a pixel unit, and a display panel. The pixel circuit includes: a driving sub-circuit, configured to generate driving current based on a data signal and a first voltage; a first light-emitting control sub-circuit configured to receive a first control signal and the first voltage, and provide the first voltage to the driving sub-circuit under control of the first control signal; a second light-emitting control sub-circuit configured to receive a second control signal and provide driving current generated by the driving sub-circuit to an output terminal of the pixel driving circuit under control of the second control signal; a driving control sub-circuit configured to receive the second control signal and the data signal and provide the data signal to the driving sub-circuit under control of the second control signal; and a reset sub-circuit configured to receive a reset signal and a second voltage, and reset the driving sub-circuit using the second voltage under control of the reset signal.

    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS
    70.
    发明申请
    SHIFT REGISTER UNIT, GATE DRIVING CIRCUIT AND DRIVING METHOD, AND DISPLAY APPARATUS 有权

    公开(公告)号：US20180108426A1

    公开(公告)日：2018-04-19

    申请号：US15504119

    申请日：2016-08-12

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok JUN ,  Xue Dong

    IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  G11C19/18

    CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

    Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

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