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    Screen print mask for laser scribe and plasma etch wafer dicing process
    63.
    发明授权
    Screen print mask for laser scribe and plasma etch wafer dicing process 有权
    激光划片和等离子体蚀刻晶圆切割工艺的屏幕打印掩模

    公开(公告)号：US09312177B2

    公开(公告)日：2016-04-12

    申请号：US14099707

    申请日：2013-12-06

    申请人： Applied Materials, Inc.

    发明人： Prabhat Kumar ,  Brad Eaton ,  Wei-Sheng Lei ,  James S. Papanu ,  Ajay Kumar

    IPC分类号： H01L21/78 ,  H01L21/304 ,  H01L21/3065 ,  B41F15/08 ,  H01L21/67 ,  H01J37/32

    CPC分类号： H01L21/78 ,  B23K26/364 ,  B41F15/08 ,  H01J37/32091 ,  H01J37/321 ,  H01J2237/334 ,  H01L21/3043 ,  H01L21/3065 ,  H01L21/67207

    摘要： Methods of using a screen-print mask for hybrid wafer dicing using laser scribing and plasma etch described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits separated by streets involves screen-printing a patterned mask above the semiconductor wafer, the patterned mask covering the integrated circuits and exposing the streets of the semiconductor wafer. The method also involves laser ablating the streets with a laser scribing process to expose regions of the semiconductor wafer between the integrated circuits. The method also involves plasma etching the semiconductor wafer through the exposed regions of the semiconductor wafer to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

    摘要翻译： 使用激光划线和等离子体蚀刻使用用于混合晶片切割的丝网印刷掩模的方法。 在一个示例中，对具有由街道分开的多个集成电路进行切割的半导体晶片的方法涉及在半导体晶片之上丝网印刷图案化掩模，该图案化掩模覆盖集成电路并暴露半导体晶片的街道。 该方法还涉及通过激光划线工艺激光烧蚀街道，以暴露集成电路之间的半导体晶片的区域。 该方法还包括通过半导体晶片的暴露区域等离子体蚀刻半导体晶片以对集成电路进行分离。 图案化掩模在等离子体蚀刻期间保护集成电路。

    Multi-step and asymmetrically shaped laser beam scribing
    65.
    发明授权
    Multi-step and asymmetrically shaped laser beam scribing 有权
    多级和不对称形激光束划线

    公开(公告)号：US09054176B2

    公开(公告)日：2015-06-09

    申请号：US14023408

    申请日：2013-09-10

    申请人： Applied Materials, Inc.

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

    IPC分类号： H01L21/00 ,  H01L21/78 ,  H01L21/3065 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40 ,  H01L21/67

    CPC分类号： H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67207

    摘要： Methods of dicing substrates by both laser scribing and plasma etching are disclosed. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser.

    摘要翻译： 公开了通过激光划线和等离子体蚀刻来切割衬底的方法。 一种方法包括激光烧蚀材料层，具有第一辐照度的烧蚀导线，并且具有低于第一辐照度的第二辐照度。 调整为具有不同注量级的光束的多次通过或具有各种注量级的多个激光束可以用于消除掩模和IC层以暴露具有第一注量级的衬底，然后用第二注入层从沟槽底部清除再沉积的材料 注量水平 使用分束器的激光划片装置可以从单个激光器提供不同注量的第一和第二光束。

    Laser, plasma etch, and backside grind process for wafer dicing
    67.
    发明授权
    Laser, plasma etch, and backside grind process for wafer dicing 有权
    用于晶片切割的激光，等离子体蚀刻和背面研磨工艺

    公开(公告)号：US08845854B2

    公开(公告)日：2014-09-30

    申请号：US13938537

    申请日：2013-07-10

    申请人： Applied Materials, Inc.

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

    IPC分类号： H01L21/00 ,  C23F1/00 ,  C23C16/00 ,  H01L21/78

    CPC分类号： H01L21/78 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/02019 ,  H01L21/027 ,  Y10T29/5124

    摘要： Front side laser scribing and plasma etch are performed followed by back side grind to singulate integrated circuit chips (ICs). A mask is formed covering ICs formed on the wafer, as well as any bumps providing an interface to the ICs. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is then etched through the gaps in the patterned mask to advance a front of an etched trench partially through the semiconductor wafer thickness. The front side mask is removed, a backside grind tape applied to the front side, and a back side grind performed to reach the etched trench, thereby singulating the ICs.

    摘要翻译： 执行前侧激光划线和等离子体蚀刻，然后进行背面研磨以分离集成电路芯片（IC）。 形成覆盖在晶片上形成的IC的掩模，以及提供与IC的接口的任何凸块。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 图案化使得半导体晶片的区域在形成IC的薄膜层之下露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以使蚀刻沟槽的前部部分地延伸穿过半导体晶片厚度。 去除前侧面罩，施加到前侧的背面研磨带，和进行到蚀刻沟槽的后侧研磨，由此分离IC。

    WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH
    68.
    发明申请
    WAFER DICING USING HYBRID MULTI-STEP LASER SCRIBING PROCESS WITH PLASMA ETCH 有权
    使用等离子体蚀刻的混合多步激光切割工艺的抛光

    公开(公告)号：US20140120698A1

    公开(公告)日：2014-05-01

    申请号：US14148499

    申请日：2014-01-06

    申请人： Applied Materials, Inc.

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

    IPC分类号： H01L21/78

    CPC分类号： H01L21/78 ,  B23K26/0608 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/3086

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 掩模由覆盖和保护集成电路的层组成。 用多步骤激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。

    WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH
    69.
    发明申请
    WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH 有权
    使用基于FEMTOSECOND的激光和等离子体蚀刻的抛光

    公开(公告)号：US20140120697A1

    公开(公告)日：2014-05-01

    申请号：US14146887

    申请日：2014-01-03

    申请人： APPLIED MATERIALS, INC.

    发明人： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar ,  James M. Holden

    IPC分类号： H01L21/822

    CPC分类号： H01L21/822 ,  B23K26/36 ,  H01J37/32889 ,  H01J37/32899 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/67069 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

    摘要翻译： 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模，该掩模包括覆盖并保护集成电路的层。 通过激光划线工艺对掩模和半导体晶片的一部分进行构图，以提供图案化掩模，并在集成电路之间部分地形成沟槽而不通过半导体晶片。 每个沟槽都有一个宽度。 通过沟槽等离子体蚀刻半导体晶片以形成对应的沟槽延伸部分并对集成电路进行分割。 每个相应的沟槽延伸部具有宽度。