公开(公告)号：US20220311393A1

公开(公告)日：2022-09-29

申请号：US17213084

申请日：2021-03-25

申请人： SYNAPTICS INCORPORATED

发明人： Dan SHEN ,  Jinbao LAN ,  Yunfu ZHANG ,  Lorenzo CRESPI

IPC分类号： H03F3/217

摘要： Various techniques are provided to reduce common mode disturbance associated with an amplifier, such as a class D amplifier. In one example, an amplifier includes a power stage configured to generate first and second PWM signals. The amplifier further includes an integration stage comprising input nodes configured to receive an input differential analog signal. The integration stage is configured to generate an output differential analog signal in response to the PWM signals and the input differential analog signal. The amplifier further includes an active compensation circuit configured to provide a compensation signal to the integration stage to reduce disturbances at the input nodes associated with the PWM signals switching between a common mode and a differential mode. Additional devices, systems, and methods are also provided.

公开(公告)号：US11456715B1

公开(公告)日：2022-09-27

申请号：US17565370

申请日：2021-12-29

申请人： Synaptics Incorporated

发明人： Yutaka Saeki

IPC分类号： G06F3/0484 ,  G06F3/0488 ,  G06F3/0485 ,  H03F3/45 ,  G09G3/20

摘要： An operational amplifier includes an output transistor having a gate coupled to an output node, at least one intermediate transistor each having a common gate node, an input transistor having a gate coupled to an input node, and a load device coupled to sources of the output transistor, the at least one intermediate transistor, and the input transistor. The operational amplifier further includes an output stage coupled to the output node, configured to drive the voltage on the output node based on currents through the output transistor, the at least one intermediate transistors, and the input transistor. The operational amplifier further includes a first switch coupled between the common gate node of the at least one intermediate transistor and the gate of the input transistor, and a second switch coupled between the output node and the common gate node of the at least one intermediate transistors.

公开(公告)号：US11448739B2

公开(公告)日：2022-09-20

申请号：US16750970

申请日：2020-01-23

申请人： Synaptics Incorporated

发明人： Mark E. Miller

IPC分类号： H04B10/00 ,  G01S7/4865 ,  G01S17/32

摘要： A time-of-flight sensor includes a light source to transmit periodic bursts light in a direction of one or more objects and an array of optical sensing elements to detect light reflected from the one or more objects and generate sensor data corresponding to the detected light. A distance calculator determines depth information of the one or more objects by determining a general phase shift of the reflected light relative to the transmitted light based on a first frame of the sensor data and a second frame of the sensor data, calculating an incremental phase shift of the reflected light relative to the transmitted light based on a linear relationship between the first frame and the second frame in relation to the general phase shift, and combining the general phase shift with the incremental phase shift to determine an actual phase shift of the reflected light relative to the transmitted light.

公开(公告)号：US11443671B2

公开(公告)日：2022-09-13

申请号：US17148364

申请日：2021-01-13

申请人： Synaptics Incorporated

发明人： Hirobumi Furihata ,  Tomoo Minaki ,  Masao Orio ,  Takashi Nose

IPC分类号： G09G3/20

摘要： A display driver includes control circuitry and image processing circuitry. The control circuitry is configured to store a default gamma curve and determine a scaling factor based on a location of a target pixel in a display panel. The control circuitry is further configured to determine a modified gamma curve by scaling the default gamma curve with the scaling factor. The image processing circuitry configured to apply a gamma transformation based on the modified gamma curve to image data defined for the target pixel to generate output voltage data for the target pixel.

公开(公告)号：US11436962B2

公开(公告)日：2022-09-06

申请号：US17148388

申请日：2021-01-13

申请人： Synaptics Incorporated

发明人： Hirobumi Furihata ,  Masao Orio ,  Takashi Nose ,  Akio Sugiyama

IPC分类号： G09G3/20

摘要： A display driver includes control circuitry and image processing circuitry. The control circuitry is configured to store first and second predetermined gamma curve defined for first and second regions of a display panel, respectively, the first region having a different pixel layout than the second region. The control circuitry is further configured to determine first and second modified gamma curves by scaling the first and second predetermined gamma curves with a common scale factor. The image processing circuitry is configured to apply a first gamma transformation based on the first modified gamma curve to a first graylevel defined for a first pixel circuit located in the first region to determine a first output voltage level and apply a second gamma transformation based on the second modified gamma curve to a second graylevel defined for a second pixel circuit located in the second region to determine a second output voltage level.

公开(公告)号：US11423819B1

公开(公告)日：2022-08-23

申请号：US17496751

申请日：2021-10-07

申请人： Synaptics Incorporated

发明人： Hirobumi Furihata ,  Takashi Nose ,  Masao Orio

IPC分类号： G09G3/20

摘要： A display driver includes image processing circuitry and drive circuitry. The image processing circuitry is configured to receive first subpixel data for a first scan line of a display panel. The display panel includes a first region with a first pixel layout and a second region with a second pixel layout different from the first pixel layout. The image processing circuitry is further configured to determine an overshoot amount based, at least in part, on the first subpixel data and region indication data and generate resulting voltage data using the overshoot amount. The region indication data indicates whether the resulting voltage data is for the first region or for the second region. The drive circuitry is configured to drive the display panel based, at least in part, on the resulting voltage data.

公开(公告)号：US20220252648A1

公开(公告)日：2022-08-11

申请号：US17170074

申请日：2021-02-08

申请人： Synaptics Incorporated

发明人： Shinobu Nohtomi

IPC分类号： G01R27/26 ,  G06F3/044 ,  H03K17/96 ,  G06F3/041

摘要： A processing system includes a level shifter, a drive circuit, and a capacitive sensing circuit. The level shifter is configured to generate a first level-shifted output corresponding to a graylevel value and a second level-shifted output corresponding to capacitive sensing control data. The drive circuit is configured to generate an output voltage based at least in part on the first level-shifted output. The capacitive sensing circuit is configured to receive a resulting signal from a sensor electrode and generate, based at least in part on the second level-shifted output, a capacitive sensing output corresponding to the resulting signal.

公开(公告)号：US20220223081A1

公开(公告)日：2022-07-14

申请号：US17148388

申请日：2021-01-13

申请人： Synaptics Incorporated

发明人： Hirobumi Furihata ,  Masao Orio ,  Takashi Nose ,  Akio Sugiyama

IPC分类号： G09G3/20

摘要： A display driver includes control circuitry and image processing circuitry. The control circuitry is configured to store first and second predetermined gamma curve defined for first and second regions of a display panel, respectively, the first region having a different pixel layout than the second region. The control circuitry is further configured to determine first and second modified gamma curves by scaling the first and second predetermined gamma curves with a common scale factor. The image processing circuitry is configured to apply a first gamma transformation based on the first modified gamma curve to a first graylevel defined for a first pixel circuit located in the first region to determine a first output voltage level and apply a second gamma transformation based on the second modified gamma curve to a second graylevel defined for a second pixel circuit located in the second region to determine a second output voltage level.

公开(公告)号：US11372780B2

公开(公告)日：2022-06-28

申请号：US16426496

申请日：2019-05-30

申请人： Synaptics Incorporated

发明人： Pontus Evert Lidman ,  Xiao William Cheng ,  Hongjie Guan ,  Jingliang Li

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06N3/08

摘要： A secure processing system includes a memory having a secure partition and a non-secure partition, a neural network processing unit (NPU) configured to initiate transactions with the memory, and a memory protection unit (MPU) configured to filter the transactions. Each of the transactions includes at least an address of the memory to be accessed, one of a plurality of first master identifiers (IDs) associated with the NPU, and security information indicating whether the NPU is in a secure state or a non-secure state when the transaction is initiated. The MPU is to selectively deny access to the secure partition of the memory based at least in part on the memory address, the first master ID, and the security information associated with each of the transactions.

公开(公告)号：US11366685B2

公开(公告)日：2022-06-21

申请号：US16685989

申请日：2019-11-15

申请人： Synaptics Incorporated

发明人： Pontus Evert Lidman ,  Jingliang Li

IPC分类号： G06F13/00 ,  G06F9/46 ,  G06F9/445 ,  G06F9/48 ,  G06F9/448 ,  G06F9/4401 ,  G06F9/54

摘要： A processing system including a processor, a first memory, a state machine configured to transition between a plurality of states, and an access filter. The first memory stores instructions that are executable by the processor, where execution of the instructions causes the processor to initiate transactions with one or more hardware resources. The access filter may filter the transactions initiated by the processor by selectively denying access to the hardware resources based at least in part on a current state of the state machine. The access filter may also filter transactions initiated by one or more of the hardware resources based at least in part on the current state of the state machine.