公开(公告)号：US20090140340A1

公开(公告)日：2009-06-04

申请号：US12365863

申请日：2009-02-04

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage.

Abstract translation: 公开了一种静电放电（ESD）保护装置结构。 ESD保护装置包括：至少第一导电型金属氧化物半导体（MOS），其中第一导电型MOS的漏极和源极分别电连接到第一电力端子和第二电力端子; 至少第二导电型扩散区域; 以及至少设置在所述第一导电型MOS与所述第二导电型扩散区之间的虚拟栅极，所述伪栅极的栅极长度小于所述第一导电型MOS栅极的栅极长度，使得所述第二导电型MOS栅极 导电型扩散区域和第一导电型MOS的漏极具有低击穿电压。

公开(公告)号：US07531903B2

公开(公告)日：2009-05-12

申请号：US11218456

申请日：2005-09-02

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/02 ,  H01L23/528 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01082

Abstract: An interconnection structure for a pad region of the substrate is provided. A semiconductor circuit and a pad are disposed on the substrate of the pad region. The interconnection structure includes a first and a second dielectric layers, via plugs and contact plugs. The patterned conductive layer includes an auxiliary layer having a plurality of gaps and a plurality of first wire lines disposed between the auxiliary layers passes through the gaps and exits from the pad region. The first dielectric layer is disposed between the patterned conductive layer and the pad. The via plugs are disposed in the first dielectric layer for connecting the auxiliary layer and the pad. The second dielectric layer is disposed between the substrate and the patterned conductive layer. The contact plugs are disposed in the second dielectric layer for electrically connecting the semiconductor circuit and the first wire lines.

Abstract translation: 提供了用于衬底的焊盘区域的互连结构。 半导体电路和焊盘设置在焊盘区域的衬底上。 互连结构包括第一和第二电介质层，通过插塞和接触插塞。 图案化导电层包括具有多个间隙的辅助层，并且设置在辅助层之间的多个第一布线通过间隙并从焊盘区域离开。 第一介电层设置在图案化的导电层和焊盘之间。 通孔插头设置在第一电介质层中，用于连接辅助层和衬垫。 第二介电层设置在基板和图案化的导电层之间。 接触插头设置在第二电介质层中，用于电连接半导体电路和第一线。

公开(公告)号：US07531374B2

公开(公告)日：2009-05-12

申请号：US11470631

申请日：2006-09-07

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L21/00

CPC classification number: H01L27/14689 ,  H01L27/14643

Abstract: A CMOS image sensor (CIS) process is described. A semiconductor substrate is provided, and then a gate dielectric layer, a gate material layer and a thickening layer are sequentially formed on the substrate, wherein the thickening layer includes at least a hard mask layer. The thickening layer is defined to form a transfer-gate pattern, and then the transfer-gate pattern is used as an etching mask to pattern the gate material layer and form a transfer gate. Ion implantation is then conducted to form a PN diode in the substrate with the transfer-gate pattern and the transfer gate as a mask.

Abstract translation: 描述CMOS图像传感器（CIS）处理。 提供半导体衬底，然后在衬底上依次形成栅介电层，栅极材料层和增厚层，其中增厚层至少包括硬掩模层。 增稠层被定义为形成转移栅极图案，然后使用转移栅极图案作为蚀刻掩模来图案化栅极材料层并形成转移栅极。 然后进行离子注入以在衬底中形成PN二极管，其中转移栅极图案和转移栅极作为掩模。

公开(公告)号：US20090072326A1

公开(公告)日：2009-03-19

申请号：US12252343

申请日：2008-10-15

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L29/06

CPC classification number: H01L29/7835 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816

Abstract: An ultra high voltage MOS transistor device includes a substrate; a source region formed in the substrate; a first doping region formed in the substrate and bordering upon the source region; a first ion well encompassing the source region and the first doping region; a gate oxide layer formed on the source region and on the first ion well; a field oxide layer connected with the gate oxide layer and formed on a semiconductor region; a dielectric layer stacked on the field oxide layer; a drain region formed at one side of the field oxide layer and being spaced apart from the source region; a second ion well encompassing the drain region; and a gate disposed on the gate oxide layer and laterally extending to the field oxide layer and onto the dielectric layer.

Abstract translation: 超高压MOS晶体管器件包括：衬底; 形成在所述基板中的源极区域; 形成在所述衬底中并与所述源极区域接壤的第一掺杂区域; 包括所述源区和所述第一掺杂区的第一离子阱; 形成在所述源极区域和所述第一离子阱上的栅极氧化物层; 与所述栅极氧化层连接并形成在半导体区域上的场氧化物层; 堆叠在场氧化物层上的电介质层; 漏极区，形成在所述场氧化物层的一侧并且与所述源极区间隔开; 包围漏区的第二离子阱; 以及设置在栅极氧化物层上并横向延伸到场氧化物层和介电层上的栅极。

公开(公告)号：US07470945B2

公开(公告)日：2008-12-30

申请号：US11565849

申请日：2006-12-01

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L31/062 ,  H01L31/113

CPC classification number: H01L27/14636 ,  H01L27/14603 ,  H01L27/14609

Abstract: A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node structure includes a P-well in the substrate within the floating node area, an N-well in the substrate outside of the floating node region, a lightly N-doped region having a portion in the P-well and another portion connected with the N-well, a heavily N-doped region in the N-well, and a contact plug for coupling the heavily N-doped region to the source follower transistor.

Abstract translation: 基于衬底并且包括转移晶体管，复位晶体管，源极跟随器晶体管，选择晶体管，光电二极管和浮动节点结构来描述CMOS图像传感器。 衬底包括传输晶体管和复位晶体管之间的浮动节点区域。 浮动节点结构包括在浮动节点区域内的衬底中的P阱，在浮动节点区域外的衬底中的N阱，具有在P阱中的一部分的轻N掺杂区域和连接到其中的另一部分 与N阱中的N阱中的高N掺杂区域和用于将重N掺杂区域耦合到源极跟随器晶体管的接触插塞。

公开(公告)号：US20080258188A1

公开(公告)日：2008-10-23

申请号：US11738836

申请日：2007-04-23

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L31/113 ,  H01L31/062

CPC classification number: H01L27/14689 ,  H01L27/14609 ,  H01L27/14643

Abstract: A method of fabricating an MOS device is provided. First, gates and source/drain regions of transistors are formed on a substrate. A photodiode doped region and a floating node doped region are formed in the substrate. Thereafter, a spacer stacked layer including a bottom layer, an inter-layer and a top layer is formed to cover each gate of the transistors. Afterwards, a first mask layer having an opening exposing at least the photodiode doped region is formed on the substrate, and then the top layer exposed by the opening is removed. Next, the first mask layer is removed, and then a second mask layer is formed on a region correspondingly exposed by the opening. A portion of the top layer and the inter-layer exposed by the second mask layer is removed to form spacers on sidewalls of the gates.

Abstract translation: 提供一种制造MOS器件的方法。 首先，晶体管的栅极和源极/漏极区域形成在衬底上。 在衬底中形成光电二极管掺杂区域和浮动节点掺杂区域。 此后，形成包括底层，层间和顶层的间隔层叠层，以覆盖晶体管的每个栅极。 之后，在衬底上形成具有至少暴露于光电二极管掺杂区域的开口的第一掩模层，然后除去由开口露出的顶层。 接下来，去除第一掩模层，然后在由开口相应地暴露的区域上形成第二掩模层。 去除由第二掩模层暴露的顶层和内层的一部分，以在栅极的侧壁上形成间隔物。

公开(公告)号：US20080217666A1

公开(公告)日：2008-09-11

申请号：US11683059

申请日：2007-03-07

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L31/113 ,  H01L31/18

CPC classification number: H01L27/14643 ,  H01L27/1463 ,  H01L27/14689

Abstract: A floating node structure of a CMOS image sensor disposed in a floating node region defined by an isolation structure of a substrate is described. The floating node structure comprises an n-doped region within the floating node region, a p-well surrounding the periphery and the bottom of the n-doped region in the substrate within the folating node region, a surface passivation layer disposed at least on the surface of the p-well, and a contact plug coupling the n-doped region to a source follower transistor of the CMOS image sensor.

Abstract translation: 描述了设置在由衬底的隔离结构限定的浮动节点区域中的CMOS图像传感器的浮动节点结构。 所述浮动节点结构包括所述浮动节点区域内的n掺杂区域，围绕所述叶酸化节点区域内的所述衬底中的所述n掺杂区域的外围和底部的p阱，至少设置在所述浮选节点区域中的表面钝化层 p阱的表面和将n掺杂区域耦合到CMOS图像传感器的源极跟随器晶体管的接触插塞。

公开(公告)号：US20080128768A1

公开(公告)日：2008-06-05

申请号：US11565849

申请日：2006-12-01

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14603 ,  H01L27/14609

Abstract: A CMOS image sensor is described, based on a substrate and including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, a photodiode and a floating node structure. The substrate includes a floating node area between the transfer transistor and the reset transistor. The floating node structure includes a P-well in the substrate within the floating node area, an N-well in the substrate outside of the floating node region, a lightly N-doped region having a portion in the P-well and another portion connected with the N-well, a heavily N-doped region in the N-well, and a contact plug for coupling the heavily N-doped region to the source follower transistor.

Abstract translation: 基于衬底并且包括转移晶体管，复位晶体管，源极跟随器晶体管，选择晶体管，光电二极管和浮动节点结构来描述CMOS图像传感器。 衬底包括传输晶体管和复位晶体管之间的浮动节点区域。 浮动节点结构包括在浮动节点区域内的衬底中的P阱，在浮动节点区域外的衬底中的N阱，具有在P阱中的一部分的轻N掺杂区域和连接到其中的另一部分 与N阱中的N阱中的高N掺杂区域和用于将重N掺杂区域耦合到源极跟随器晶体管的接触插塞。

公开(公告)号：US20080038911A1

公开(公告)日：2008-02-14

申请号：US11874928

申请日：2007-10-19

Applicant: Ching-Hung Kao ,  Chin-Shun Lin

Inventor： Ching-Hung Kao ,  Chin-Shun Lin

IPC: H01L21/20

CPC classification number: H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

Abstract: The invention is directed to a method for manufacturing a field plate of a high voltage device. The field plate is located on a drift region of a substrate, wherein an isolation structure is located on the drift region. The method comprises steps of forming a first dielectric layer over the substrate and then forming a first patterned conductive layer on the first dielectric layer, wherein the first patterned conductive layer is located over the isolation structure and exposes a portion of a top surface of the first dielectric layer. The exposed portion of the first dielectric layer is removed until a top surface of the isolation structure so as to form a plurality of vertical fin-type dielectric bottoms.

Abstract translation: 本发明涉及一种用于制造高压装置的场板的方法。 场板位于衬底的漂移区上，其中隔离结构位于漂移区上。 该方法包括以下步骤：在衬底上形成第一电介质层，然后在第一电介质层上形成第一图案化导电层，其中第一图案化导电层位于隔离结构上方，并暴露第一电介质层的顶表面的一部分 电介质层。 去除第一电介质层的暴露部分，直到隔离结构的顶表面形成多个垂直翅片型电介质底部。

公开(公告)号：US20070232010A1

公开(公告)日：2007-10-04

申请号：US11760789

申请日：2007-06-10

Applicant: Ching-Hung Kao

Inventor： Ching-Hung Kao

IPC: H01L21/36

CPC classification number: H01L27/0811 ,  H01L27/0808 ,  H01L29/7391 ,  H01L29/93

Abstract: A junction varactor includes a gate finger lying across an ion well of a semiconductor substrate; a gate dielectric situated between the gate finger and the ion well; a first ion diffusion region with first conductivity type located in the ion well at one side of the gate finger, the first ion diffusion region serving as an anode of the junction varactor; and a second ion diffusion region with a second conductivity type located in the ion well at the other side of the gate finger, the second ion diffusion region serving as a cathode of the junction varactor. In operation, the gate of the junction varactor is biased to a gate voltage VG that is not equal to 0 volt.

Abstract translation: 结型变容二极管包括位于半导体衬底的离子阱上的栅极指状物; 位于栅指和离子阱之间的栅电介质; 具有第一导电类型的第一离子扩散区域位于栅极指一侧的离子阱中，第一离子扩散区域用作接合变容二极管的阳极; 以及位于栅指的另一侧的离子阱中的具有第二导电类型的第二离子扩散区，第二离子扩散区用作结变异反应器的阴极。 在操作中，接合变容二极管的栅极偏置为不等于0伏的栅极电压V SUB。