知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

567 records (took 0.025 seconds)

    Semiconductor memory device and method for biasing dummy line therefor
    64.
    发明授权
    Semiconductor memory device and method for biasing dummy line therefor 有权
    用于偏置虚拟线的半导体存储器件和方法

    公开(公告)号：US07405960B2

    公开(公告)日：2008-07-29

    申请号：US11695232

    申请日：2007-04-02

    Applicant: Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

    Inventor： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

    IPC: G11C11/00

    CPC classification number: G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

    Abstract: A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

    Abstract translation: 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR BIASING DUMMY LINE THEREFOR
    70.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR BIASING DUMMY LINE THEREFOR 有权
    半导体存储器件和用于偏置其直线的方法

    公开(公告)号：US20080112208A1

    公开(公告)日：2008-05-15

    申请号：US11695232

    申请日：2007-04-02

    Applicant: Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

    Inventor： Beak-Hyung Cho ,  Hyung-Rok Oh ,  Chang-Soo Lee

    IPC: G11C11/34 ,  G11C11/00 ,  G11C5/06

    CPC classification number: G11C13/0007 ,  G11C7/14 ,  G11C11/1655 ,  G11C11/1657 ,  G11C13/0004 ,  G11C2213/32 ,  G11C2213/72

    Abstract: A semiconductor memory device and a dummy line biasing method in which in the semiconductor memory device of a diode structure including a plurality of memory cells each having one variable resistance device and one diode device, the memory device includes a plurality of normal word lines, a plurality of normal bit lines, at least one or more dummy word lines and at least one or more dummy bit lines. The plurality of normal word lines are each arrayed in a first direction as a length direction. The plurality of normal bit lines are each arrayed in a second direction as a width direction, intersected with the first direction, so that the plurality of normal bit lines are intersected with the normal word lines. At least one or more dummy word lines are arrayed in the same structure as the normal word lines in the first direction, the at least one or more dummy word lines having a constant level of applied voltage. At least one or more dummy bit lines are arrayed in the same structure as the normal bit lines in the second direction, the at least one or more dummy bit lines being maintained in a floating state. Leakage current in the semiconductor memory device can be reduced, and a production yield can be enhanced.

    Abstract translation: 一种半导体存储器件和虚拟线偏置方法，其中在包括多个存储单元的半导体存储器件的半导体存储器件中，每个存储器单元均具有一个可变电阻器件和一个二极管器件，该存储器件包括多个正常字线， 多个正常位线，至少一个或多个虚拟字线和至少一个或多个虚拟位线。 多个正常字线分别作为长度方向排列在第一方向上。 多个正常位线分别以与第一方向相交的宽度方向的第二方向排列，使得多个正常位线与正常字线相交。 至少一个或多个虚拟字线以与第一方向上的正常字线相同的结构排列，至少一个或多个虚拟字线具有恒定的施加电压水平。 至少一个或多个虚拟位线以与第二方向上的正常位线相同的结构排列，至少一个或多个虚拟位线保持在浮置状态。 可以减少半导体存储器件中的泄漏电流，并且可以提高生产率。

Patent Agency Ranking