公开(公告)号：US07265689B2

公开(公告)日：2007-09-04

申请号：US11017568

申请日：2004-12-20

Applicant: Chung-Yen Lu

Inventor： Chung-Yen Lu

IPC: H03M5/00

CPC classification number: H04L25/4915

Abstract: The present invention provides a data transformation apparatus for transforming a first data block into a second data block. The first data block comprises a predetermined number of bits. The data transformation apparatus comprises a control bit module, a processing module, and a selection module. The control bit module is used for generating a plurality of control bit sets, wherein each control bit set represents a transformation procedure of the first data block. The processing module is used for receiving the first data block and the plural control bit sets, and accordingly for generating a plurality of first reference values. The selection module connects with the processing module and generates the second data block according to the plural first reference values and a predetermined judgment value.

Abstract translation: 本发明提供了一种用于将第一数据块变换为第二数据块的数据变换装置。 第一数据块包括预定数量的位。 数据变换装置包括控制位模块，处理模块和选择模块。 控制位模块用于产生多个控制位集合，其中每个控制位集合表示第一数据块的变换过程。 处理模块用于接收第一数据块和多个控制位集合，并且因此用于生成多个第一参考值。 选择模块与处理模块连接，并根据多个第一参考值和预定的判断值生成第二数据块。

公开(公告)号：US07262715B2

公开(公告)日：2007-08-28

申请号：US10334435

申请日：2002-12-31

Applicant: Raghavendra P. Sagar

Inventor： Raghavendra P. Sagar

IPC: H03M5/00

CPC classification number: H04N1/00

Abstract: According to some embodiments, a bit stuffing method is provided for fax and other data communication.

Abstract translation: 根据一些实施例，提供了用于传真和其他数据通信的位填充方法。

公开(公告)号：US07230550B1

公开(公告)日：2007-06-12

申请号：US11383506

申请日：2006-05-16

Applicant: Udar Mittal ,  James P. Ashley

Inventor： Udar Mittal ,  James P. Ashley

IPC: H03M5/00

CPC classification number: H03M13/27

Abstract: A system (100) and method (200) of combining codewords is provided. The system can include a splitter (120) for splitting a first codeword (110) into a most significant bits part MSP (112) and a least significant bits part LSP (114), a combiner (130) for combining the MSP of the first codeword with a second codeword to produce a first group (132), and a concatenator (140) for concatenating the first group with the LSP to produce a second group (134), and multiplexing the first group with the second group to produce a multiplexed codeword (150). Bit-errors in the LSP correspond to decoding errors only in a codeword associated with the LSP, and not to decoding errors in other codewords.

Abstract translation: 提供了组合码字的系统（100）和方法（200）。 该系统可以包括用于将第一码字（110）分割成最高有效位部分MSP（112）和最低有效位部分LSP（114）的分离器（120），用于组合第一 具有第二码字的码字以产生第一组（132），以及用于将所述第一组与所述LSP连接以产生第二组（134）的级联器（140），并且将所述第一组与所述第二组多路复用 码字（150）。 LSP中的位错误仅对应于与LSP相关联的码字中的解码错误，而不解码其他码字中的错误。

公开(公告)号：US07154417B2

公开(公告)日：2006-12-26

申请号：US11273707

申请日：2005-11-14

Applicant: Akira Mashimo

Inventor： Akira Mashimo

IPC: H03M5/00

CPC classification number: G11B20/1426 ,  G11B2020/1457 ,  G11B2220/2579

Abstract: In an optical disk apparatus, the polarity of synchronization information is adaptively set to thereby improve the quality of data recording and reproduction. When inserting and recording synchronization information, an encoder of an optical disk apparatus temporarily sets the polarity of the synchronization information to either a mark or a space in accordance with a predetermined rule. A DSV which is obtained if the synchronization information is to be recorded with the polarity which has been temporarily set is computed. If the DSV which is computed is equal to or smaller than a predetermined limit value, the polarity which has been temporarily set is accepted and the synchronization information is actually recorded with the polarity. If the DSV which is computed exceeds the limit value, on the other hand, the polarity which has been temporarily set is not adopted, and the synchronization information is actually recorded with a polarity which is different from the polarity.

Abstract translation: 在光盘装置中，自适应地设定同步信息的极性，从而提高数据记录和再现的质量。 当插入和记录同步信息时，光盘装置的编码器根据预定规则将同步信息的极性临时设置为标记或空格。 计算如果要以暂时设定的极性来记录同步信息所获得的DSV。 如果计算出的DSV等于或小于预定极限值，则临时设置的极性被接受，并且实际上以极性记录同步信息。 另一方面，如果计算出的DSV超过限制值，则不采用临时设定的极性，实际上以与极性不同的极性记录同步信息。

公开(公告)号：US07120666B2

公开(公告)日：2006-10-10

申请号：US10285315

申请日：2002-10-30

Applicant: Steven McCanne ,  Michael J. Demmer

Inventor： Steven McCanne ,  Michael J. Demmer

IPC: G06F15/16 ,  H03M5/00 ,  G06G12/04

CPC classification number: H04L67/2828 ,  H04L67/28 ,  H04L67/2852 ,  H04L67/288 ,  H04L67/289 ,  H04L69/329

Abstract: In a network having transaction acceleration, for an accelerated transaction, a client directs a request to a client-side transaction handler that forwards the request to a server-side transaction handler, which in turn provides the request, or a representation thereof, to a server for responding to the request. The server sends the response to the server-side transaction handler, which forwards the response to the client-side transaction handler, which in turn provides the response to the client. Transactions are accelerated by the transaction handlers by storing segments of data used in the transactions in persistent segment storage accessible to the server-side transaction handler and in persistent segment storage accessible to the client-side transaction handler. When data is to be sent between the transaction handlers, the sending transaction handler compares the segments of the data to be sent with segments stored in its persistent segment storage and replaces segments of data with references to entries in its persistent segment storage that match or closely match the segments of data to be replaced. The receiving transaction store reconstructs the data sent by replacing segment references with corresponding segment data from its persistent segment storage, requesting missing segments from the sender as needed. The transaction accelerators could handle multiple clients and/or multiple servers and the segments stored in the persistent segment stores can relate to different transactions, different clients and/or different servers. Persistent segment stores can be prepopulated with segment data from other transaction accelerators.

Abstract translation: 在具有事务加速的网络中，对于加速事务，客户端将请求引导到客户端事务处理程序，该客户端事务处理程序将请求转发到服务器端事务处理程序，服务器端事务处理程序又将请求或其表示提供给 服务器来响应请求。 服务器将响应发送到服务器端事务处理程序，该处理程序将响应转发给客户端事务处理程序，后者又向客户端提供响应。 事务处理程序通过将事务中使用的数据段存储在服务器端事务处理程序可访问的持久段存储器中，以及客户端事务处理程序可访问的持久段存储中来加速事务处理。 当在事务处理程序之间发送数据时，发送事务处理程序将要发送的数据的段与存储在其持久段存储中的段进行比较，并且通过引用其持久段存储中匹配或紧密的条目替换数据段 匹配要替换的数据段。 接收事务存储器通过用来自其持久段存储器的相应段数据替换段引用来重构发送的数据，根据需要从发送方请求丢失段。 交易加速器可以处理多个客户端和/或多个服务器，并且存储在持久性段存储中的段可以涉及不同的事务，不同的客户端和/或不同的服务器。 可以使用来自其他事务加速器的段数据预先存储持久性段存储。

公开(公告)号：US07098817B2

公开(公告)日：2006-08-29

申请号：US11036146

申请日：2005-01-14

Applicant: William P. Cornelius ,  William C. Athas

Inventor： William P. Cornelius ,  William C. Athas

IPC: H03M5/00

CPC classification number: G06F13/4027 ,  H03M13/23 ,  H03M13/41

Abstract: Methods and apparatus for spreading and concentrating information to constant-weight encode data words on a parallel data line bus while allowing communication of information across sub-word paths. In one embodiment, data transfer rates previously obtained only with differential architectures are achieved by only a small increase in line count above single ended architectures. For example, an 18-bit data word requires 22 encoded data lines for transmission, where previously, 16 and 32 lines would be required to transmit un-coded data with single-ended and differential architectures respectively. Constant-weight parallel encoding maintains constant current in the parallel-encoded data lines and the high and low potential driver circuits for the signal lines.

Abstract translation: 用于扩展和集中信息以在并行数据线总线上对数据字进行恒权重编码的方法和装置，同时允许跨越子字路径的信息通信。 在一个实施例中，仅通过差分架构获得的数据传输速率仅通过单端架构上的行数小幅增加来实现。 例如，18位数据字需要22个用于传输的编码数据线，其中先前需要16行和32行才能以单端和差分架构传输未编码的数据。 恒定并行编码在并行编码数据线和信号线的高电平和低电位驱动电路中保持恒定电流。

公开(公告)号：US07091887B2

公开(公告)日：2006-08-15

申请号：US11056349

申请日：2005-02-10

Applicant: Yuji Nagai ,  Yutaka Kashihara ,  Tadashi Kojima

Inventor： Yuji Nagai ,  Yutaka Kashihara ,  Tadashi Kojima

IPC: H03M5/00 ,  G11B7/0045

CPC classification number: G11B20/00086 ,  G11B20/0021 ,  G11B20/00362 ,  G11B20/00492 ,  G11B20/00579 ,  G11B20/00927 ,  G11B2020/1457

Abstract: A modulator includes a replacement processing unit which replaces a part of main information code-converted in a main information converter with specific information code-converted in a specific information converter and a direct-current component suppress processing unit which performs direct-current component suppress processing for the main information which has undergone the replacement processing in the replacement processing unit. The direct-current component suppress processing can be performed for the main information after the replacement processing of the main information with the specific information to prevent deterioration in direct-current component suppress characteristics due to the replacement processing.

Abstract translation: 调制器包括替换处理单元，该替换处理单元将特定信息转换器中的特定信息代码转换的主信息代码转换的一部分替换为特定信息转换器中的代码转换器，以及执行直流分量抑制处理的直流分量抑制处理单元 对于在替换处理单元中进行了替换处理的主要信息。 可以对具有特定信息的主信息的替换处理之后的主信息执行直流分量抑制处理，以防止由替换处理引起的直流分量抑制特性的劣化。

公开(公告)号：US07084789B2

公开(公告)日：2006-08-01

申请号：US10715077

申请日：2003-11-17

Applicant: Chandra C. Varanasi ,  Kinhing P. Tsang

Inventor： Chandra C. Varanasi ,  Kinhing P. Tsang

IPC: H03M7/00 ,  H03M5/00

CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1457

Abstract: A method and apparatus are provided for encoding and decoding digital information. A sequence of data words is received, wherein each data word has a running digital sum (RDS). The sequence of data words is encoded into a sequence of corresponding code words, which has a current RDS. For each data word a binary symbol is added to the data word and the data word is selectively complemented as a function of the RDS of the data word and the current RDS of the sequence of code words to form the corresponding code word.

Abstract translation: 提供了一种用于对数字信息进行编码和解码的方法和装置。 接收数据字序列，其中每个数据字具有运行数字和（RDS）。 数据字的序列被编码成具有当前RDS的相应代码字的序列。 对于每个数据字，将二进制符号添加到数据字，并且数据字被选择性地补充为数据字的RDS和代码字序列的当前RDS的函数，以形成相应的代码字。

公开(公告)号：US07075461B2

公开(公告)日：2006-07-11

申请号：US10793819

申请日：2004-03-08

Applicant: Jong-Seok Kim

Inventor： Jong-Seok Kim

IPC: H03M5/00

CPC classification number: H03M5/04 ,  H04L1/24 ,  H04L25/4906

Abstract: A method of generating an 8B/10B-like code bit sequence that is similar to an 8B/10B code may include: generating a parallel pseudo random bit sequence having N bits wherein N is an integer and N≧2; and transforming the parallel pseudo random bit sequence into a parallel first bit sequence that is similar to an 8B/10B code, a number Q of consecutive “0”s or “1”s of the first bit sequence being Q≦M1, wherein Q and M1 are integers and M

Abstract translation: 生成类似于8B / 10B码的8B / 10B类码比特序列的方法可以包括：产生具有N比特的并行伪随机比特，其中N是整数，N> = 2; 并且将并行伪随机比特序列变换成类似于8B / 10B代码的并行第一比特序列，第一比特序列的连续“0”或“1”的数目Q为Q <= M 1， 其中Q和M1是整数，M

公开(公告)号：US20060114136A1

公开(公告)日：2006-06-01

申请号：US10536648

申请日：2003-11-26

Applicant: Shiqiang Chu ,  Richard Shen

Inventor： Shiqiang Chu ,  Richard Shen

IPC: H03M5/00

CPC classification number: H04N19/188 ,  H04N19/12 ,  H04N19/136 ,  H04N19/44 ,  H04N19/46 ,  H04N19/70 ,  H04N21/4343 ,  H04N21/440218

Abstract: The present invention provides an apparatus and method for switching between particular decoders within a plurality of decoders, each decoder adapted to decode bit streams having a unique format. The apparatus comprises format detectors which output format indicators based on information from the bit stream. Logic responsive to the format detector output may determine a particular decoder among the plurality of decoders. The particular decoder determined by the logic decodes the formatted bit stream. At least one switch, responsive to the determination of the logic, connects the formatted bit stream to the particular decoder. The format detectors detect at least one of the frame information, or start code, the packet header information, and the code word values in a portion of a coded content of the bit stream, wherein the code word values, derivatives thereof, or a pattern of word values, are unique to the bit stream format.

Abstract translation: 本发明提供一种用于在多个解码器内的特定解码器之间切换的装置和方法，每个解码器适于解码具有唯一格式的位流。 该装置包括格式检测器，其基于来自比特流的信息输出格式指示符。 响应于格式检测器输出的逻辑可以确定多个解码器中的特定解码器。 由逻辑器确定的特定解码器对格式化的比特流进行解码。 响应于逻辑的确定，至少一个开关将格式化的比特流连接到特定解码器。 格式检测器检测比特流的编码内容的一部分中的帧信息或起始码，分组头信息和码字值中的至少一个，其中码字值，其导数或模式 的字值，是比特流格式唯一的。