公开(公告)号：US08081019B2

公开(公告)日：2011-12-20

申请号：US12292721

申请日：2008-11-21

申请人： Aaron Jungreis

发明人： Aaron Jungreis

IPC分类号： H03B19/00

CPC分类号： H02M1/15 ,  H02J3/383 ,  H02M1/12 ,  H02M1/4208 ,  Y02B70/126 ,  Y02E10/563

摘要： An apparatus for generating a compensation signal for a power converter where the second harmonic ripple on the voltage bus is substantially removed from the compensation signal. The apparatus comprises a frequency-locked clock generator, a bus voltage data generator, a stack, and a compensation signal generator. The frequency-locked clock is coupled to the power converter voltage bus that contains harmonics of the AC line frequency. The clock generator frequency locks to the second harmonic of the AC line frequency and creates a system clock which is used for the synchronous operations throughout the apparatus. The bus-voltage data generator inputs a power converter scaled-bus voltage, generates bus-voltage data at a sampling rate which is determined by the coupled system clock. The output of the bus-voltage generator is input into a stack. The output of the stack is coupled to a summer to remove the second harmonic ripple, and is used by a modified PID′ filter to generate a compensation signal for a power converter controller.

摘要翻译： 一种用于产生功率转换器的补偿信号的装置，其中电压总线上的二次谐波纹波基本上从补偿信号中去除。 该装置包括频率锁定时钟发生器，总线电压数据发生器，堆栈和补偿信号发生器。 频率锁定时钟耦合到包含AC线路频率谐波的功率转换器电压总线。 时钟发生器频率锁定到AC线路频率的二次谐波，并创建一个系统时钟，用于整个设备的同步操作。 总线电压数据发生器输入功率转换器缩放总线电压，以由耦合的系统时钟确定的采样率产生总线电压数据。 总线电压发生器的输出被输入到堆栈中。 堆叠的输出耦合到加法器以去除二次谐波纹波，并且被修改的PID'滤波器用于为功率转换器控制器生成补偿信号。

公开(公告)号：US08060766B2

公开(公告)日：2011-11-15

申请号：US12399736

申请日：2009-03-06

申请人： Georgios K. Konstadinidis ,  Sudhakar Bobba

发明人： Georgios K. Konstadinidis ,  Sudhakar Bobba

IPC分类号： G06F1/00 ,  H03B19/00

CPC分类号： G06F1/305 ,  G06F1/08 ,  G06F1/3203

摘要： A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

摘要翻译： 用于微处理器的电压下降监视和校正电路包括：监视器电路，被配置为监视微处理器的电压下降并执行暂时的跳时技术以补偿电压下降。 用于监视和校正微处理器的电压下降的方法包括：监视微处理器的电压下降; 并执行临时跳时技术以补偿电压下降。 计算机系统包括存储器; 可操作地连接到存储器的处理器; 以及存储在存储器中的计算机可读指令，用于使处理器：监视微处理器的电压下降; 并执行临时的时钟跳跃技术来补偿电压下降。

公开(公告)号：US07978785B2

公开(公告)日：2011-07-12

申请号：US11677400

申请日：2007-02-21

申请人： Curtis Leifso

发明人： Curtis Leifso

IPC分类号： H03B19/00

CPC分类号： H03B19/14 ,  H03B2200/0036 ,  H03B2200/0078

摘要： The present invention provides an improved frequency doubling circuit, with adjustable phase offset. Briefly, rather than using the traditional equations cos (2ωt)=cos 2(ωt)−sin 2(ωt) and sin(2ωt)=2 sin(ωt)cos(ωt), the quadrature output signals are generated utilizing mixers, each having two input signals, separated in phase by the same offset. This minimizes the effects of the non-linearities introduced by the mixer, which therefore reduces amplitude mismatch between the quadrature signals. Also, the phase offset of the quadrature output signals can be tuned and calibrated using a phase shifting circuit. This phase shifting circuit realizes a tuning range of approximately 5° in programmable steps. This combination of circuits can be used to minimize the amplitude mismatch and phase errors, thereby reducing the amplitude of and interference caused by transmission of the image frequency to the receivers input.

摘要翻译： 本发明提供了具有可调相位偏移的改进的倍频电路。 简而言之，不是使用传统方程cos（2ωt）= cos 2（ωt）-sin 2（ωt）和sin（2ωt）= 2sin（ωt）cos（ωt），正交输出信号是利用混频器产生的， 具有两个输入信号，其相位偏移相同。 这使得由混频器引入的非线性的影响最小化，因此减小正交信号之间的幅度失配。 此外，正交输出信号的相位偏移可以使用移相电路进行调谐和校准。 该相移电路在可编程步骤中实现大约5°的调谐范围。 电路的这种组合可用于最小化幅度失配和相位误差，从而减少由图像频率传输到接收器输入引起的幅度和干扰。

公开(公告)号：US07969251B2

公开(公告)日：2011-06-28

申请号：US12821893

申请日：2010-06-23

申请人： Zhuo Fu ,  Susumu Hara

发明人： Zhuo Fu ,  Susumu Hara

IPC分类号： H03B19/00

CPC分类号： H03L7/18 ,  H03K23/667 ,  H03L7/081 ,  H03L7/1976

摘要： A divider control circuit includes a first and a second delta sigma modulator configured to generate a divider control signal for a fractional-N divider and a fractional signal indicative of a phase error in the divider output. The fractional signal is supplied for control of an interpolator circuit. The divider control circuit may be implemented as a look-ahead circuit where two or more divider control signals and fractional signals are generated during a single cycle to allow the divider control circuit to be run at a reduced clock rate.

摘要翻译： 分频器控制电路包括被配置为产生用于分数N分频器的分频器控制信号和指示分频器输出中的相位误差的分数信号的第一和第二ΔΣ调制器。 提供分数信号用于控制内插器电路。 除法器控制电路可以被实现为在单个周期期间产生两个或更多个除法器控制信号和分数信号的先行电路，以允许分频器控制电路以降低的时钟速率运行。

公开(公告)号：US07952399B1

公开(公告)日：2011-05-31

申请号：US12355872

申请日：2009-01-19

申请人： Roland Cadotte, Jr.

发明人： Roland Cadotte, Jr.

IPC分类号： H03B19/00

CPC分类号： H03K23/425 ,  H03K19/09421

摘要： A frequency divider circuit includes a master-slave flip-flop having a master flip-flop and a slave flip-flop. The slave flip-flop is connected to the master flip-flop. The master flip-flop includes a first plurality of logic gates and is configured to receive a first clock signal. The slave flip-flop includes a second plurality of logic gates and is configured to receive a second clock signal. The second plurality of logic gates is implemented using single-ended diode-transistor logic (DTL).

摘要翻译： 分频器电路包括具有主触发器和从触发器的主从触发器。 从触发器连接到主触发器。 主触发器包括第一多个逻辑门，并且被配置为接收第一时钟信号。 从触发器包括第二多个逻辑门，并且被配置为接收第二时钟信号。 使用单端二极管晶体管逻辑（DTL）来实现第二多个逻辑门。

公开(公告)号：US20110025381A1

公开(公告)日：2011-02-03

申请号：US12902904

申请日：2010-10-12

申请人： Seiji YAMAHIRA

发明人： Seiji YAMAHIRA

IPC分类号： H03K21/00 ,  H03B19/00 ,  H03B19/06

CPC分类号： G06F1/06 ,  H03K5/135 ,  H03K5/15013 ,  H03K23/425

摘要： A divider circuit for dividing the frequency of a multi-phase clock signal, which can ensure a sufficient data latch time even if the multi-phase clock signal has a high frequency, includes a main latch circuit which generates an inverted data signal using, for example, two of eight clock signals of an eight-phase clock signal, and a sub-latch circuit which uses the eight clock signals as a trigger to receive the inverted data signal as a common data signal.

摘要翻译： 用于分割多相时钟信号的频率的分频电路，即使多相时钟信号具有高频率也能够确保足够的数据锁存时间，包括主锁存电路，其产生反相数据信号，用于 例如，八相时钟信号的八个时钟信号中的两个，以及使用八个时钟信号作为触发来接收反相数据信号作为公共数据信号的子锁存电路。

公开(公告)号：US07830184B2

公开(公告)日：2010-11-09

申请号：US11659023

申请日：2005-07-27

申请人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

发明人： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC分类号： H03B19/00

CPC分类号： G06F7/68

摘要： A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

摘要翻译： 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

公开(公告)号：US07812648B2

公开(公告)日：2010-10-12

申请号：US11936008

申请日：2007-11-06

申请人： John Wood

发明人： John Wood

IPC分类号： H03B19/00

CPC分类号： H03L7/0995 ,  H03K23/54 ,  H03K23/546 ,  H03L7/0998

摘要： A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results.

摘要翻译： 一种使用具有多相振荡器的多个相位信号的时钟源的分频器。 在一个版本中，分隔器包括连接以形成环的多个点移动级。 点移动阶段是在清除前一阶段的同时提升一个或零个阶段的阶段。 根据阶段的数量和时钟的相位数，通过所有级进行点，确定分频比。 在另一个实施例中，多个锁存元件设置有分割输入，并且每个锁存元件与多相振荡器的相位重新计时。 锁存元件的输出被组合在电容器阵列中以产生输出波形。 还公开了一种与分频器结合使用的内插器。 当内插器放置在PLL的反馈路径中时，会产生分数倍频/分频。

公开(公告)号：US20100240323A1

公开(公告)日：2010-09-23

申请号：US12407700

申请日：2009-03-19

申请人： Dongjiang Qiao ,  Frederic Bossu

发明人： Dongjiang Qiao ,  Frederic Bossu

IPC分类号： H04B1/40 ,  H03B19/00

CPC分类号： G06F1/06 ,  H03K23/667 ,  H03K23/68

摘要： A synchronized frequency divider that can divide a clock signal in frequency and provide differential output signals having good signal characteristics is described. In one exemplary design, the synchronized frequency divider includes a single-ended frequency divider and a synchronization circuit. The single-ended frequency divider divides the clock signal in frequency and provides first and second single-ended signals, which may be complementary signals having timing skew. The synchronization circuit resamples the first and second single-ended signals based on the clock signal and provides differential output signals having reduced timing skew. In one exemplary design, the synchronization circuit includes first and second switches and first and second inverters. The first switch and the first inverter form a first sample-and-hold circuit or a first latch that resamples the first single-ended signal. The second switch and the second inverter form a second sample-and-hold circuit or a second latch that resamples the second single-ended signal.

摘要翻译： 描述了可以将时钟信号分频并提供具有良好信号特性的差分输出信号的同步分频器。 在一个示例性设计中，同步分频器包括单端分频器和同步电路。 单端分频器分频时钟信号，并提供第一和第二单端信号，这可能是具有定时偏移的互补信号。 同步电路基于时钟信号重新采样第一和第二单端信号，并提供具有减小的定时偏差的差分输出信号。 在一个示例性设计中，同步电路包括第一和第二开关以及第一和第二逆变器。 第一开关和第一反相器形成第一采样保持电路或重新采样第一单端信号的第一锁存器。 第二开关和第二反相器形成第二采样保持电路或重新采样第二单端信号的第二锁存器。

公开(公告)号：US20100207669A1

公开(公告)日：2010-08-19

申请号：US12388544

申请日：2009-02-19

申请人： Sheng-Chun Chueh ,  Wei-Jen Huang

发明人： Sheng-Chun Chueh ,  Wei-Jen Huang

IPC分类号： H03B19/00

CPC分类号： H03L7/08

摘要： The invention relates to a frequency adjusting apparatus and the method therefor comprising an adjusting module, a comparing module, a processing module and an operating module. The adjusting module generates a frequency signal according to a predetermined signal after receiving a trigger signal and generates N adjusting signal according to N processing signal. The comparing module compares the N adjusting signal with the predetermined signal according to a predetermined manner and generates N comparing result. The processing module generates N processing signal according to the N comparing result. The operating module executes a specific operation with M adjusting signal of the N adjusting signal matching the predetermined rule and generates a operation signal, wherein the frequency of the operation signal is approximately equal to which of the predetermined signal. Wherein N and M are natural numbers and N≧M≧1, the adjusting module adjusts the operation frequency according to the operation signal.

摘要翻译： 本发明涉及一种频率调节装置及其方法，包括调整模块，比较模块，处理模块和操作模块。 调整模块在接收到触发信号之后根据预定信号产生频率信号，并根据N处理信号产生N个调整信号。 比较模块根据预定的方式将N调整信号与预定信号进行比较，并产生N个比较结果。 处理模块根据N个比较结果产生N个处理信号。 操作模块执行具有与预定规则匹配的N调整信号的M调整信号的特定操作，并产生操作信号，其中操作信号的频率近似等于预定信号中的哪一个。 其中N和M是自然数，N≥M≥1，调节模块根据操作信号调节操作频率。