公开(公告)号：US20150263712A1

公开(公告)日：2015-09-17

申请号：US14632204

申请日：2015-02-26

申请人： Rockwell Automation Limited

发明人： Philip J. Agar ,  Mitchell Couper

IPC分类号： H03K5/125 ,  H03K23/00

CPC分类号： H03K5/125 ,  G01R31/2829 ,  G05B23/0235 ,  G05B2219/23201 ,  H03K5/08 ,  H03K21/023 ,  H03K23/00

摘要： A method of monitoring an analogue signal output from a sensor comprising comparing the amplitude of the analogue signal to a first high and low threshold, setting a primary monitoring signal to a first value when the amplitude of the analogue signal exceeds the first high threshold, setting the primary monitoring signal to a second value when the amplitude of the analogue signal decreases below the first low threshold, comparing the amplitude of the analogue signal to a second high and low threshold, setting a secondary monitoring signal to a first value when the amplitude of the analogue signal exceeds the second high threshold, setting the secondary monitoring signal to a second value when the amplitude of the analogue signal decreases below the second low threshold, comparing the primary and secondary monitoring signals and determining from the comparison whether an error exists with the monitoring of the analogue signal.

摘要翻译： 一种监测从传感器输出的模拟信号的方法，包括将模拟信号的幅度与第一高低阈值进行比较，当模拟信号的幅度超过第一高阈值时，将初级监测信号设置为第一值，设置 当所述模拟信号的幅度降低到低于所述第一低阈值时，所述主监视信号为第二值，将所述模拟信号的幅度与第二高低阈值进行比较，当所述模拟信号的振幅为 模拟信号超过第二高阈值，当模拟信号的幅度降低到低于第二低阈值时，将辅助监控信号设置为第二值，比较主要和次要监控信号，并从比较中确定是否存在与 监控模拟信号。

公开(公告)号：US09118332B2

公开(公告)日：2015-08-25

申请号：US13818381

申请日：2011-08-03

申请人： Lucien Garcia ,  Jérôme Hou

发明人： Lucien Garcia ,  Jérôme Hou

IPC分类号： G04F10/04 ,  H03K23/00 ,  H03K21/40 ,  H03K21/02

CPC分类号： H03K23/00 ,  G04F10/04 ,  H03K21/023 ,  H03K21/40

摘要： A method for measuring a period of time between a first event and a second event via a hardware counter 2 and of a software counter 3. A digital counter 1 using such a method is also described.

摘要翻译： 一种用于经由硬件计数器2和软件计数器3测量第一事件和第二事件之间的时间段的方法。还描述了使用这种方法的数字计数器1。

公开(公告)号：US20140270048A1

公开(公告)日：2014-09-18

申请号：US14200317

申请日：2014-03-07

申请人： Microchip Technology Incorporated

发明人： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

IPC分类号： H03K23/00

CPC分类号： H03K23/00 ,  G01P3/481 ,  G01P3/486 ,  G01P3/487 ,  G01P3/488 ,  G01P3/489 ,  H02P6/17 ,  H03K21/38 ,  H03K23/40

摘要： A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

摘要翻译： 数字周期分配器具有具有R个最低有效位（LSB）和P个最高有效位（MSB）的第一计数器，其具有计数输入和复位输入，其中所述计数输入接收第一时钟信号，并且所述复位输入接收第二时钟 信号; 具有P位并与第一计数器的P位耦合的锁存器; 具有P位和计数输入和复位输入的第二计数器，其中所述计数输入接收所述第一时钟信号; 以及第一比较器，用于将锁存器的P位与第二计数器的P位进行比较并产生输出信号，其中输出信号也被馈送到第二计数器的复位输入。

公开(公告)号：US08723579B2

公开(公告)日：2014-05-13

申请号：US13738476

申请日：2013-01-10

申请人： Seiko Instruments Inc.

发明人： Yasushi Imai

IPC分类号： H03K3/00

CPC分类号： H03K23/00 ,  H03K23/42

摘要： The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

摘要翻译： 定时生成电路包括由三个T触发器电路构成的二进制计数器，并且二进制计数器的复位时的二进制状态也用于系统复位和产生输出脉冲，以产生具有不同定时的八个输出脉冲 由二进制计数器产生的8个二进制状态，并包括复位状态。 在系统复位时，二进制计数器的复位信号被延迟，使得在二进制计数器的复位时解码器电路的输出被延迟。 因此，解码器电路的输出被快速复位信号屏蔽，从而可以防止在系统复位时解码器电路的输出反映在输出端子中。

公开(公告)号：US08542040B1

公开(公告)日：2013-09-24

申请号：US13285103

申请日：2011-10-31

申请人： Justin O'Day

发明人： Justin O'Day

IPC分类号： H03B19/00

CPC分类号： H03K23/00 ,  H03K23/667

摘要： An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.

摘要翻译： 集成电路包括：第一可变分频器电路，被配置为接收时钟信号并且响应于第一控制输入而施加较低范围的整数分频因子以产生第一分频时钟信号;以及第二可变分频器电路，被配置为接收时钟 信号并且响应于第二控制输入施加整数除数因子的上限范围以产生第二分频时钟信号。 集成电路还包括复用器电路，其被配置为响应于第三控制输入选择性地传递第一和第二分频时钟信号。

公开(公告)号：US20110254595A1

公开(公告)日：2011-10-20

申请号：US13087021

申请日：2011-04-14

申请人： Weigang Sun

发明人： Weigang Sun

IPC分类号： H03B19/06 ,  H03K3/356 ,  H03K3/00

CPC分类号： H03K3/356139 ,  H03K21/10 ,  H03K23/00

摘要： Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.

摘要翻译： 提供了触发器和分频电路的各种实施例。 一方面，触发器包括输入级和锁存级。 输入级能够在第一时钟信号和第二时钟信号的控制下将输入信号转换为输出信号。 锁存级能够在第三时钟信号和第四时钟信号的控制下锁存输出信号。 第一时钟信号，第二时钟信号，第三时钟信号和第四时钟信号具有不同的相位。

公开(公告)号：US07378885B1

公开(公告)日：2008-05-27

申请号：US11959069

申请日：2007-12-18

申请人： Marcel A. Kossel

发明人： Marcel A. Kossel

IPC分类号： H03K21/00

CPC分类号： H03K23/00

摘要： A method for dividing a plurality of multiphase signals comprising performing resetable divider stages to the plurality of multiphase signals forming a plurality of divided multiphase signals having a monotonic increasing phase with equal spacing and an ideal duty cycle of 50% through a plurality of resetable dividers, wherein the plurality of divided multiphase signals have no phase ambiguity; and producing a plurality of periodic reset signals to the plurality of resetable dividers to enable the plurality of resetable dividers to divide the plurality of multiphase signals in a timely correct sequence to form the divided multiphase signal through a reset signal generator, the plurality of periodic reset signals being produced by a combinational network of the reset signal generator, the combination network is configured for generating a number of pulses based on the plurality of multiphase signals and performing a plurality of decimation stages and wherein the periodic reset signals are generated solely in response to the plurality of multiphase signals.

摘要翻译： 一种用于将多个多相信号分离的方法，包括对多个多相信号执行可复位分频器级，所述多相信号通过多个可复位分频器形成具有相等间隔的单调增加相位和50％的理想占空比的多个分频多相信号， 其中所述多个划分的多相信号没有相位模糊度; 以及产生多个周期性复位信号给所述多个可复位分频器，以使所述多个可复位分频器能够及时正确地排列多个多相信号，以通过复位信号发生器形成分频多相信号，所述多个周期性复位 信号由复位信号发生器的组合网络产生，所述组合网络被配置为基于所述多个多相信号产生多个脉冲并且执行多个抽取级，并且其中所述周期性复位信号仅仅响应于 多个多相信号。

公开(公告)号：US07203265B2

公开(公告)日：2007-04-10

申请号：US11155523

申请日：2005-06-16

申请人： Frederick A. Perner

发明人： Frederick A. Perner

IPC分类号： H03K23/00 ,  G06M3/00

CPC分类号： H03K23/00

摘要： A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.

摘要翻译： 提供了一个用于高级应用的M位N位同步计数器。 M比特N位同步计数器包括M比特N寄存器，被配置为接收和存储对应于与被配置为从M×N寄存器顺序排列所选择的数据字的N位计数器集成的至少一个字的数据。 本设计用单个计数器锁存电路代替多个或堆叠的可选择的锁存器，并采用组合的加载/存储逻辑和计数器控制。

公开(公告)号：US20060288059A1

公开(公告)日：2006-12-21

申请号：US11155523

申请日：2005-06-16

申请人： Frederick Perner

发明人： Frederick Perner

IPC分类号： G06F15/00

CPC分类号： H03K23/00

摘要： A M by N bit synchronous counter for use in advanced applications is provided. The M by N bit synchronous counter comprises an M by N register configured to receive and store data corresponding to at least one word integrated with a N bit counter configured to sequentially count out a selected word of data from the M by N register. The present design replaces a single counter latch circuit with a plurality or stack of selectable latches and employs combined load/store logic and counter controls.

摘要翻译： 提供了一个用于高级应用的M位N位同步计数器。 M比特N位同步计数器包括M比特N寄存器，被配置为接收和存储对应于与被配置为从M×N寄存器顺序排列所选择的数据字的N位计数器集成的至少一个字的数据。 本设计用单个计数器锁存电路代替多个或堆叠的可选择的锁存器，并采用组合的加载/存储逻辑和计数器控制。

公开(公告)号：US06879202B2

公开(公告)日：2005-04-12

申请号：US10772788

申请日：2004-02-05

申请人： Andy T. Nguyen

发明人： Andy T. Nguyen

IPC分类号： G06F1/08 ,  H03K23/00 ,  H03K19/177

CPC分类号： G06F1/08 ,  H03K23/00

摘要： A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

摘要翻译： 数字频率合成器（DFS）电路在时钟路径上增加了一些额外的延迟。 输入时钟信号的真实和补码版本分别提供给第一和第二传送门。 在控制电路的方向下，通路将真实时钟信号的所选上升沿和补码时钟信号的选择的下降沿传送到DFS电路的输出时钟端。 当不通过真实和补码时钟信号时，保持器电路保留已经存在于输出时钟端子上的值。 在一些实施例中，两个通过的门都可被禁用，并且接地或功率高的信号可被施加到输出端。 其他实施例包括其中使用DFS电路以允许每个可编程逻辑块的单独时钟控制的PLD。