公开(公告)号：US20030233517A1

公开(公告)日：2003-12-18

申请号：US10170122

申请日：2002-06-12

Inventor： Nathan L. Goldshlag

IPC: G06F012/00

CPC classification number: H03M9/00 ,  G11C7/1036 ,  G11C7/1051 ,  G11C2207/107

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract translation: 用于产生一个或多个串行比特流的电路包括耦合到重新格式化器的存储器，其又耦合到串行器，用于将并行数据转换成串行数据。 存储器包括具有用于存储一个或多个串行位流的已知位宽（例如，32位）的多个字。 每个串行比特流的长度通常不是存储器的位宽的整数倍，导致存储每个串行比特流的最后一个字包含间隙。 重新格式化器通过将来自位流的最后一个字的位与来自第一个字的位组合来提供一个完全填充的字给序列化器来消除每个这样的间隙。 随着操作的进行，重新格式化器继续组合来自连续单词的位，以确保产生完全填充的单词。 由此消除了以前在产生串行比特流时出现的间隙。

公开(公告)号：US20030200416A1

公开(公告)日：2003-10-23

申请号：US10448934

申请日：2003-05-30

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G06F012/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US20030200381A1

公开(公告)日：2003-10-23

申请号：US10449581

申请日：2003-05-30

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G06F012/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US20030196070A1

公开(公告)日：2003-10-16

申请号：US10452744

申请日：2003-06-02

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G06F012/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（ 14 ）用作视频帧存储器的特征的存储器电路（ 14 ）。 存储器电路（ 14 ）在输入和输出数据端口上包含一个具有缓冲区（ 18,20 ）的动态随机存取存储器阵列（ 24 ） （ 22 ），以允许对存储器阵列的异步读取，写入和刷新访问（ 24 ）。 存储器电路（ 14 ）被串行和随机访问。 地址生成器（ 28 ）包含存储随机存取地址和地址排序器（ 40 ）的地址缓冲寄存器（ 36 ） 存储器阵列的地址流（ 24 ）。 地址流的初始地址是存储在地址缓冲寄存器（ 36 ）中的随机存取地址。

公开(公告)号：US20030196067A1

公开(公告)日：2003-10-16

申请号：US10452339

申请日：2003-06-02

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G06F012/00

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（ 14 ）用作视频帧存储器的特征的存储器电路（ 14 ）。 存储器电路（ 14 ）在输入和输出数据端口上包含一个具有缓冲区（ 18,20 ）的动态随机存取存储器阵列（ 24 ） （ 22 ），以允许对存储器阵列的异步读取，写入和刷新访问（ 24 ）。 存储器电路（ 14 ）被串行和随机访问。 地址生成器（ 28 ）包含存储随机存取地址和地址排序器（ 40 ）的地址缓冲寄存器（ 36 ） 存储器阵列的地址流（ 24 ）。 地址流的初始地址是存储在地址缓冲寄存器（ 36 ）中的随机存取地址。

公开(公告)号：US20030147288A1

公开(公告)日：2003-08-07

申请号：US10068596

申请日：2002-02-05

Inventor： Mary E. Hackbarth ,  Rodney W. Roark ,  Donald J. Verhaeghe ,  Dennis C. Young

IPC: G11C007/00

CPC classification number: G11C7/1036 ,  G11C11/22

Abstract: A method for accessing data in a serial ferroelectric memory device including an input shift register coupled to a ferroelectric memory array including a plurality of memory cells arranged in a number of rows and columns thereof, the memory array having associated row, column, and segment decoders, includes clocking a serial address into the input shift register and starting a read access before the serial address is completely shifted into the input shift register. A read access can be started before an input bit sequence containing row, column, and segment decoder addresses has been completely clocked into the memory.

Abstract translation: 一种用于访问串行强电介质存储器件中的数据的方法，包括耦合到强电介质存储器阵列的输入移位寄存器，所述输入移位寄存器包括以多个行和列排列的多个存储器单元，所述存储器阵列具有相关联的行，列和段解码器 包括将串行地址计时到输入移位寄存器，并在串行地址完全移入输入移位寄存器之前启动读访问。 可以在包含行，列和段解码器地址的输入位序列已经完全计入存储器之前开始读访问。

公开(公告)号：US20030002378A1

公开(公告)日：2003-01-02

申请号：US10227430

申请日：2002-08-26

Applicant: FUJITSU LIMITED

Inventor： Toshiya Uchida ,  Hiroyuki Kobayashi

IPC: G11C008/00

CPC classification number: G11C7/1036 ,  G11C7/1006

Abstract: A semiconductor memory device capable of shortening the command supply interval during random access and thus improving the transfer rate of input/output data. In response to a write command, identical data is written into multiple memory banks having identical addresses assigned thereto. At this time, a bank selection circuit sequentially selects the memory banks to initiate write operations in a staggered manner. Since the write operation can be started before all memory banks become idle, the interval between the supply of read command and the supply of write command can be shortened. Consequently, the number of commands supplied per given time can be increased, and since data signal can be input/output more frequently than in conventional devices, the data transfer rate (data bus occupancy) improves. As a result, the performance of a system to which the semiconductor memory device is mounted can be enhanced.

Abstract translation: 一种半导体存储器件，其能够缩短随机存取期间的指令供给间隔，从而提高输入/输出数据的传送速率。 响应于写入命令，将相同的数据写入具有分配给其的相同地址的多个存储体。 此时，存储体选择电路按顺序选择存储体以交错方式开始写入操作。 由于可以在所有存储体空闲之前开始写入操作，所以可以缩短读取命令的供给与写入命令的供给之间的间隔。 因此，可以增加每给定时间提供的命令数，并且由于数据信号可以比常规设备更频繁地输入/输出，所以数据传输速率（数据总线占用）提高。 结果，可以提高安装半导体存储器件的系统的性能。

公开(公告)号：US20020093844A1

公开(公告)日：2002-07-18

申请号：US09756953

申请日：2001-01-09

Inventor： Warren Kurt Howlett

IPC: G11C019/00

CPC classification number: G11C7/1036 ,  G11C7/1042 ,  G11C15/00 ,  G11C19/00

Abstract: M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Abstract translation: M个并行数据流被交织到一个串行比特流中，并被移入一个分段寄存器，所以所有数据流的位零都在第一位和第（X-1）位移位。 Mth数据流的所有位占据与具有每个宽度为X的M个存储器寄存器的目标存储器件互连的均匀间隔的非相邻存储器元件。存储器件的第M个存储器寄存器被寻址，同时将所有互连的位写入第M个存储器寄存器 在一个时钟周期内。 然后将比特流移位一个存储器元件，使得（M-1）个并行数据流的位占据互连存储器元件，寄存器地址递减，并且互连位同时写入第（M-1）个寄存器 。 该过程重复直到在M个时钟周期的经过时间内写入M个寄存器。 阅读基本上以相反的顺序发生。

公开(公告)号：US20010009532A1

公开(公告)日：2001-07-26

申请号：US09812820

申请日：2001-03-21

Inventor： Haruki Toda ,  Shozo Saito ,  Kaoru Tokushige

IPC: G11C008/00

CPC classification number: G11C7/1036 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107

Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

公开(公告)号：US6119175A

公开(公告)日：2000-09-12

申请号：US093531

申请日：1998-06-08

Applicant: Juka Mikko Hakkarainen ,  Nga Cheung Lee ,  Chung-Yih Ho

Inventor： Juka Mikko Hakkarainen ,  Nga Cheung Lee ,  Chung-Yih Ho

IPC: G11C7/10 ,  G11C19/00 ,  G11C19/28 ,  G06F12/00

CPC classification number: G11C19/28 ,  G11C19/00 ,  G11C7/1036

Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

Abstract translation: 配置为在ASIC环境中实现的通信单元仅使用少量的芯片表面积并且需要最小数量的引脚。 该单元相对于ASIC内部时钟异步工作，使得通信可以独立于这种内部时钟发生。 在一个实施例中，通信单元包括经由数据总线耦合到移位寄存器的控制器。 与控制器的引脚连接包括请求线REQ，输入/输出控制线I / O（或INOUT），确认线ACK，外部时钟线EXTCLK和数据线DATA。 移位寄存器还经由数据总线耦合到存储器模块，例如RAM。 ASIC处理器通过控制线耦合到控制器，移位寄存器和存储器模块。