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    Semiconductor device
    51.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US07482647B2

    公开(公告)日：2009-01-27

    申请号：US11768514

    申请日：2007-06-26

    申请人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    发明人： Susumu Inoue ,  Yo Takeda ,  Yutaka Maruo

    IPC分类号： H01L31/113

    CPC分类号： H01L31/02164 ,  H01L23/552 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor element that is set up on a semiconductor layer, a light shielding wall that is set up around the semiconductor element, a hole that is set up on the light shielding wall, and a wiring layer that is electrically connected to the semiconductor element and is drawn out through the hole to the outside of the light shielding wall. The wiring layer has a pattern including a first part that is located within the hole and a second part that is located on the outside of the hole and has a larger width compared to the width of the first part, the width of the second part being the same with or larger than the width of the hole.

    Semiconductor device having nonvolatile memory device with improved charge holding property
    52.
    发明授权
    Semiconductor device having nonvolatile memory device with improved charge holding property 失效
    具有具有改善的电荷保持特性的非易失性存储器件的半导体器件

    公开(公告)号：US07473962B2

    公开(公告)日：2009-01-06

    申请号：US11330870

    申请日：2006-01-12

    申请人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

    发明人： Yutaka Maruo ,  Susumu Inoue ,  Yo Takeda

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11521 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11558

    摘要： A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.

    摘要翻译： 半导体器件包括：半导体层; 第一区域和第二区域，其由设置在所述半导体层上的分离绝缘层划定; 设置在所述第一区域上的非易失性存储器; 设置在所述第二区域上的多个MOS晶体管; 嵌入在所述第二区域上的所述多个MOS晶体管之间的第一层间绝缘层; 以及设置在所述第一区域和所述第二区域上方的第二层间绝缘层。 第二层间绝缘层被设置为如同覆盖第一区域上的非易失性存储器，并且在第二区域上设置在第一层间绝缘层的上方，就像覆盖MOS晶体管一样。

    Non-volatile memory device
    53.
    发明授权
    Non-volatile memory device 失效
    非易失性存储器件

    公开(公告)号：US07005328B2

    公开(公告)日：2006-02-28

    申请号：US10939330

    申请日：2004-09-14

    申请人： Akihiko Ebina ,  Susumu Inoue

    发明人： Akihiko Ebina ,  Susumu Inoue

    IPC分类号： H01L21/82

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

    摘要： A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

    摘要翻译： 具有存储单元的半导体器件。 每个存储单元具有形成在半导体衬底上的字栅，其中插入有第一栅极绝缘层，杂质层以及具有侧壁形状的第一和第二控制栅极。 将杂质层相互相邻的第一和第二控制栅极连接到公共接触部分。 公共接触部分包括第一接触导电层，第二接触导电层和焊盘形第三接触导电层。 第三接触导电层形成在第一和第二接触导电层上。

    Semiconductor device and method of fabricating the same
    54.
    发明授权
    Semiconductor device and method of fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06972456B2

    公开(公告)日：2005-12-06

    申请号：US10636562

    申请日：2003-08-08

    申请人： Susumu Inoue

    发明人： Susumu Inoue

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

    摘要： A semiconductor device having a memory region formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each non-volatile memory device has a word gate formed above a semiconductor layer with a gate insulating layer interposed, an impurity layer formed in the semiconductor layer to form a source region or a drain region, and control gates formed in the form of side walls formed along both side surfaces of the word gate. Each control gate includes a first control gate and a second control gate in mutual contact, where the first and second control gates are respectively formed on charge accumulation layers of different thicknesses.

    摘要翻译： 一种半导体器件，具有由多个行和列的矩阵排列的非易失性存储器件形成的存储区域。 每个非易失性存储器件具有形成在半导体层之上的字栅，栅极绝缘层被插入，形成在半导体层中以形成源区或漏区的杂质层和形成为侧壁形式的控制栅 沿字门的两侧面形成。 每个控制栅极包括相互接触的第一控制栅极和第二控制栅极，其中第一和第二控制栅极分别形成在不同厚度的电荷累积层上。

    Method of manufacturing a semiconductor device
    55.
    发明申请
    Method of manufacturing a semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20050101065A1

    公开(公告)日：2005-05-12

    申请号：US10956005

    申请日：2004-09-30

    申请人： Susumu Inoue

    发明人： Susumu Inoue

    IPC分类号： H01L27/10 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

    摘要： A method of manufacturing a semiconductor device includes: a step of forming a bottom oxide film on a silicon substrate in a memory transistor formation region and a peripheral circuit transistor formation region; a step of forming a nitride film on the bottom oxide film; a step of forming a top oxide film on the nitride film; a step of removing the top oxide film, the nitride film and the bottom oxide film from the peripheral circuit transistor formation region to expose a surface of the silicon substrate in the peripheral circuit transistor formation region; and a step of forming a gate oxide film on the silicon substrate in the peripheral circuit transistor formation region.

    摘要翻译： 一种制造半导体器件的方法包括：在存储晶体管形成区域和外围电路晶体管形成区域中的硅衬底上形成底部氧化物膜的步骤; 在底部氧化膜上形成氮化物膜的步骤; 在氮化膜上形成顶部氧化膜的步骤; 从外围电路晶体管形成区域去除顶部氧化膜，氮化物膜和底部氧化膜的步骤，以暴露外围电路晶体管形成区域中的硅衬底的表面; 以及在外围电路晶体管形成区域中的硅衬底上形成栅极氧化膜的步骤。

    Information processing system
    56.
    发明授权
    Information processing system 有权
    信息处理系统

    公开(公告)号：US06872139B2

    公开(公告)日：2005-03-29

    申请号：US09988217

    申请日：2001-11-19

    申请人： Masaki Sato ,  Susumu Inoue

    发明人： Masaki Sato ,  Susumu Inoue

    IPC分类号： A63F13/12 ,  A63F13/10 ,  G06F3/00 ,  G06F3/02 ,  G06F3/033 ,  G06F13/12 ,  H04Q9/00 ,  A63F13/00

    CPC分类号： A63F13/22 ,  A63F13/10 ,  A63F13/235 ,  A63F13/77 ,  A63F2300/1025 ,  A63F2300/1031

    摘要： When setting (changing) a reception mode in a receiving unit 40, a CPU 62 issues a reception mode command to the receiving unit 40. Having received the command, a serial interface 53 writes the command to a command buffer 52. A protocol controller 50 analyzes the command which has been written to the command buffer 52 to determine whether the reception mode is a FIX mode or an UNFIX mode, and writes a corresponding status (a device ID, unique ID, mode, etc.) to a status memory 54. Then, when data is received from a transmission unit 20, the receiving unit 40 refers to the status which has been written to determine whether or not the received data is from a transmission system which has been set.

    摘要翻译： 当在接收单元40中设置（改变）接收模式时，CPU 62向接收单元40发出接收模式命令。接收到该命令后，串行接口53将命令写入命令​​缓冲器52.协议控制器50 分析已经写入命令缓冲器52的命令，以确定接收模式是FIX模式还是UNFIX模式，并将相应的状态（设备ID，唯一ID，模式等）写入状态存储器54 然后，当从发送单元20接收到数据时，接收单元40参考已经写入的状态来确定接收的数据是否来自已经设置的发送系统。

    Method of fabricating semiconductor device
    57.
    发明授权
    Method of fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06787417B2

    公开(公告)日：2004-09-07

    申请号：US10614985

    申请日：2003-07-09

    申请人： Susumu Inoue

    发明人： Susumu Inoue

    IPC分类号： H01L218247

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11543

    摘要： A method of fabricating a semiconductor device in accordance with the present invention relates to a method of fabricating a semiconductor device including a memory region and a logic circuit region having a peripheral circuit, the method including the steps of: patterning a predetermined region formed of a stopper layer and a first conductive layer within the memory region, without patterning the logic circuit region; forming control gates in the form of side walls over both side surfaces of the first conductive layer within at least the memory region, with an ONO film interposed in between; forming first side wall dielectric layers on upper portions of the control gates; forming a gate electrode for a MOS transistor by patterning the first conductive layer within the logic circuit region; and forming a second side wall dielectric layer over the gate electrode and the side surfaces of the control gates and the first side wall dielectric layers.

    摘要翻译： 根据本发明的制造半导体器件的方法涉及一种制造半导体器件的方法，所述半导体器件包括存储区域和具有外围电路的逻辑电路区域，所述方法包括以下步骤：将由 阻挡层和存储区内的第一导电层，而不构图逻辑电路区域; 在至少所述存储区域内在所述第一导电层的两个侧表面上形成侧壁形式的控制栅，其中介于其间的ONO膜; 在所述控制栅极的上部形成第一侧壁电介质层; 通过对逻辑电路区域内的第一导电层进行构图来形成用于MOS晶体管的栅电极; 以及在栅电极和控制栅极和第一侧壁电介质层的侧表面上形成第二侧壁电介质层。

    Input device
    59.
    发明授权
    Input device 有权
    输入设备

    公开(公告)号：US08554960B2

    公开(公告)日：2013-10-08

    申请号：US12821558

    申请日：2010-06-23

    申请人： Susumu Inoue ,  Haruki Tojo

    发明人： Susumu Inoue ,  Haruki Tojo

    IPC分类号： G06F3/00 ,  G06F3/033 ,  G01N31/10 ,  G01N33/00 ,  G01C9/00 ,  G01C17/00 ,  G01C19/00

    CPC分类号： A63F13/23 ,  A63F13/211 ,  A63F13/24 ,  A63F2300/1025 ,  A63F2300/1043 ,  A63F2300/105 ,  G06F3/0346 ,  G06F3/038

    摘要： In an input device, a controller for controlling an input portion and acquiring data is connected to a bus. The bus can be connected with an external expansion device via an expansion connector. The connection of the bus from the expansion connector to the controller is switched on and off by a switcher. Data acquired from a sensor having a function equivalent to that of the external expansion device is transmitted to the controller via the bus by a sensor controller which is connected to each of a side of the controller and a side of the expansion connector of the bus without interposing the switcher. The sensor controller switches the connection of the switcher off when an access to itself is made from the controller.

    摘要翻译： 在输入装置中，用于控制输入部分并获取数据的控制器连接到总线。 总线可以通过扩展连接器与外部扩展设备连接。 总线从扩展连接器到控制器的连接由切换器打开和关闭。 从具有与外部扩展装置的功能相当的功能的传感器获取的数据经由总线通过传感器控制器传送到控制器，传感器控制器连接到控制器的一侧和总线的扩展连接器的一侧， 插入切换器。 当从控制器进行访问时，传感器控制器关闭切换器的连接。