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    SCALABLE ARCHITECTURE ENABLING LARGE MEMORY SYSTEM FOR IN-MEMORY COMPUTATIONS
    51.
    发明申请
    SCALABLE ARCHITECTURE ENABLING LARGE MEMORY SYSTEM FOR IN-MEMORY COMPUTATIONS 审中-公开

    公开(公告)号：US20200225862A1

    公开(公告)日：2020-07-16

    申请号：US16828930

    申请日：2020-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan JIANG ,  Qiang PENG ,  Hongzhong ZHENG

    IPC: G06F3/06

    Abstract: A memory system provides deduplication of user data in the physical memory space of the system for user data that is duplicated in the virtual memory space of a host system. A transaction manager (TM) uses a transaction table to maintain data coherency and data concurrency for the virtual memory space. A write data engine manager (WDEM) uses an outstanding bucket number and command queues to maintain data coherency and data concurrency for the physical memory space. The WDEM receives data write requests from the TM and sends a corresponding write command to a selected command queue. A write data engine responds to a write command in a command queue by storing the data in an overflow memory region if the data is not duplicated in the virtual memory space, or by incrementing a reference counter for the data if the data is duplicated in the virtual memory space.

    QUASI-SYNCHRONOUS PROTOCOL FOR LARGE BANDWIDTH MEMORY SYSTEMS
    52.
    发明申请
    QUASI-SYNCHRONOUS PROTOCOL FOR LARGE BANDWIDTH MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20200174676A1

    公开(公告)日：2020-06-04

    申请号：US16787002

    申请日：2020-02-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG

    IPC: G06F3/06 ,  G06F13/42 ,  G06F13/16 ,  G06F15/78 ,  G06F12/02

    Abstract: A high-bandwidth memory (HBM) system includes an HBM device and a logic circuit. The logic circuit includes a first interface coupled to a host device and a second interface coupled to the HBM device. The logic circuit receives a first command from the host device through the first interface and converts the received first command to a first processing-in-memory (PIM) command that is sent to the HBM device through the second interface. The first PIM command has a deterministic latency for completion. The logic circuit further receives a second command from the host device through the first interface and converting the received second command to a second PIM command that is sent to the HBM device through the second interface. The second PIM command has a non-deterministic latency for completion.

    HBM RAS CACHE ARCHITECTURE
    53.
    发明申请
    HBM RAS CACHE ARCHITECTURE 审中-公开

    公开(公告)号：US20200004652A1

    公开(公告)日：2020-01-02

    申请号：US16150239

    申请日：2018-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin NIU ,  Krishna MALLADI ,  Hongzhong ZHENG

    IPC: G06F11/20 ,  G06F3/06

    Abstract: According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies that include a memory cell die and a logic die. The memory cell die may be configured to store data at a memory address. The logic die may include an interface to the stacked integrated circuit dies and configured to communicate memory accesses between the memory cell die and at least one external device. The logic die may include a reliability circuit configured to ameliorate data errors within the memory cell die. The reliability circuit may include a spare memory configured to store data, and an address table configured to map a memory address associated with an error to the spare memory. The reliability circuit may be configured to determine if the memory access is associated with an error, and if so completing the memory access with the spare memory.

    EFFECTIVE TRANSACTION TABLE WITH PAGE BITMAP
    56.
    发明申请
    EFFECTIVE TRANSACTION TABLE WITH PAGE BITMAP 审中-公开

    公开(公告)号：US20190073133A1

    公开(公告)日：2019-03-07

    申请号：US15821704

    申请日：2017-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongyan JIANG ,  Hongzhong ZHENG

    IPC: G06F3/06 ,  G06F12/0831 ,  G06F9/46 ,  G06F12/1009

    Abstract: A transaction manager for use with memory is described. The transaction manager can include a write data buffer to store outstanding write requests, a read data multiplexer to select between data read from the memory and the write data buffer, a command queue and a priority queue to store requests for the memory, and a transaction table to track outstanding write requests, each write request associated with a state that is Invalid, Modified, or Forwarded.

    INTELLIGENT HIGH BANDWIDTH MEMORY APPLIANCE
    57.
    发明申请
    INTELLIGENT HIGH BANDWIDTH MEMORY APPLIANCE 审中-公开

    公开(公告)号：US20190050325A1

    公开(公告)日：2019-02-14

    申请号：US15796743

    申请日：2017-10-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Krishna T. MALLADI ,  Hongzhong ZHENG ,  Robert BRENNAN ,  Hyungseuk KIM ,  Jinhyun KIM

    IPC: G06F12/02 ,  G06F12/0862

    Abstract: Inventive aspects include An HBM+ system, comprising a host including at least one of a CPU, a GPU, an ASIC, or an FPGA; and an HBM+ stack including a plurality of HBM modules arranged one atop another, and a logic die disposed beneath the plurality of HBM modules. The logic die is configured to offload processing operations from the host. A system architecture is disclosed that provides specific compute capabilities in the logic die of high bandwidth memory along with the supporting hardware and software architectures, logic die microarchitecture, and memory interface signaling options. Various new methods are provided for using in-memory processing abilities of the logic die beneath an HBM memory stack. In addition, various new signaling protocols are disclosed to use an HBM interface. The logic die microarchitecture and supporting system framework are also described.

    MEMORY DEVICES AND MODULES
    58.
    发明申请
    MEMORY DEVICES AND MODULES 审中-公开

    公开(公告)号：US20180129553A1

    公开(公告)日：2018-05-10

    申请号：US15865250

    申请日：2018-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chaohong HU ,  Hongzhong ZHENG ,  Uksong KANG ,  Zhan PING

    IPC: G06F11/10

    Abstract: An embodiment includes a memory module, comprising: a module error interface; and a plurality of memory devices, each memory device coupled to the module error interface, including a data interface and an device error interface, and configured to communicate error information through the device error interface and the module error interface.

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