公开(公告)号：US20180204495A1

公开(公告)日：2018-07-19

申请号：US15565853

申请日：2017-03-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ling Wang ,  Quanhu Li ,  Longyan Wang ,  Baoxia Zhang ,  Cuili Gai ,  Yicheng Lin

IPC: G09G3/20 ,  G11C19/28

Abstract: The embodiments of the present disclosure disclose a gate driving circuit and a display panel. In the gate driving circuit, a control unit of a shift register may input a dual pulse control signal to a first control terminal of an output unit; and the output unit outputs a scanning signal having a pulse width equal to a pulse period of the dual pulse control signal to a corresponding gate line under the control of the dual pulse control signal. In this way, the output unit is controlled by the control unit to output a scanning signal of which a pulse width may be modulated, so as to output a gate signal of which a pulse width may be modulated.

公开(公告)号：US20170039930A1

公开(公告)日：2017-02-09

申请号：US14914576

申请日：2015-08-21

Applicant: BOE Technology Group Co., Ltd.

Inventor： Quanhu Li

IPC: G09G3/20 ,  G09G3/3266 ,  G11C19/28 ,  G09G3/36

CPC classification number: G09G3/2092 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A control sub-unit, a shift register unit, a shift register, a gate driving circuit and a display apparatus. The control sub-unit comprises a low level input terminal (VGL), a selection module and N sets of nodes (Q1′, QB1′, Q2′, QB2′ . . . QN′, QBN′), each set of nodes (Q1′, QB1′, Q2′, QB2′ . . . QN′, QBN′) comprises a first control node (Q1′, Q2′, . . . QN′) and a second control node (QB1′, QB2′ . . . QBN′), when the first control node (Q1′) in one set of nodes (Q1′, QB1′) among the N sets of nodes is at a high level and the second control node (QB1′) in said one set of nodes (Q1′, QB1′) is at a low level, the selection module connects the second control nodes (QB2′ . . . QBN′) of the other N-1 sets of nodes (Q2′, QB2′ . . . QN′, QBN′) to the low level input terminal, such that the first control nodes (Q2′, . . . QN′) and the second control nodes (QB2′ . . . QBN′) in the other N-1 sets of nodes (Q2′, QB2′ . . . QN′, QBN′) are all at the low level, wherein N is a positive integer larger than 1.

Abstract translation: 控制子单元，移位寄存器单元，移位寄存器，门驱动电路和显示装置。 控制子单元包括低电平输入端子（VGL），选择模块和N组节点（Q1'，QB1'，Q2'，QB2'... QN'，QBN'），每组节点 Q1“，QB1'，Q2'，QB2'... QN'，QBN'）包括第一控制节点（Q1'，Q2'，... QN'）和第二控制节点（QB1'，QB2'）。 当Q个节点中的一组节点（Q1'，QB1'）中的第一控制节点（Q1'）处于高电平时，并且所述一个节点中的第二控制节点（QB1'）在所述一个节点 节点组（Q1'，QB1'）处于低电平，选择模块连接其他N-1个节点集合（Q2'，QB2'...）的第二控制节点（QB2'... QBN'）。 ，QN'，QBN'）到低电平输入端子，使得另一N-1中的第一控制节点（Q2'，... QN'）和第二控制节点（QB2'... QBN'） 节点组（Q2'，QB2'... QN'，QBN'都处于低电平，其中N是大于1的正整数。

公开(公告)号：US11257957B2

公开(公告)日：2022-02-22

申请号：US16620663

申请日：2018-06-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Pan Xu ,  Yicheng Lin ,  Cuili Gai ,  Baoxia Zhang ,  Quanhu Li ,  Ling Wang

IPC: H01L21/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

Abstract: The present disclosure provides a thin film transistor, a method of fabricating the same, an array substrate and a display device. The thin film transistor includes: source and drain electrodes in a same layer arranged on a base substrate; an active layer on the base substrate and in contact with the source and drain electrodes; a gate insulating layer at a side of the active layer away from the base substrate; a gate electrode at a side of the gate insulating layer away from the base substrate. Orthographic projections of the gate electrode, the source electrode and the drain electrode on the base substrate do not overlap with one another, and a region of the active layer not covered by the gate electrode, the source electrode and the drain electrode and at a side of the active layer away from the base substrate is subjected to conductorization.

公开(公告)号：US11189228B2

公开(公告)日：2021-11-30

申请号：US16630305

申请日：2019-06-05

Applicant: BOE Technology Group Co., Ltd.

Inventor： Quanhu Li ,  Yongfu Diao ,  Wenkang Wang ,  Zhongliu Yang ,  Mingjing Yang

IPC: G09G3/3258 ,  G09G3/3291

Abstract: A pixel circuit, a method for driving a pixel circuit, and a display device are provided. The pixel circuit includes: a storage circuit, a data writing circuit, a light emitting driving circuit, and a compensation circuit. The data writing circuit is configured to write a data voltage to the storage circuit under control of a scanning control signal; the storage circuit is configured to store the data voltage and enable a stored data voltage to be available to the compensation circuit for a compensation operation; the compensation circuit is configured to maintain a compensation voltage based on the stored data voltage at a control terminal of the light emitting driving circuit under control of a compensation control signal; and the light emitting driving circuit configured to drive the light emitting element to emit light under control of the compensation voltage.

公开(公告)号：US11087688B2

公开(公告)日：2021-08-10

申请号：US15779789

申请日：2017-12-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yi-Cheng Lin ,  Guang Yan ,  Quanhu Li ,  Mingi Chu

IPC: G09G3/3258

Abstract: Embodiments of the present disclosure provide a driving method for a pixel circuit. The pixel circuit includes a light emitting device and a drive transistor. The method includes: compensating the drive transistor in a first compensation manner including an internal voltage compensation during an operation period of the light emitting device; and compensating the drive transistor in a second compensation manner including the internal voltage compensation and an external voltage compensation during a non-operation period of the light emitting device.

公开(公告)号：US20200234644A1

公开(公告)日：2020-07-23

申请号：US16096796

申请日：2018-01-17

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yongqian Li ,  Pan Xu ,  Quanhu Li

IPC: G09G3/3258

Abstract: The present application provides a pixel driving circuit, including a driving sub-circuit, a compensation sub-circuit, a first switching sub-circuit, and a second switching sub-circuit. The driving sub-circuit has a control terminal electrically connected to a first terminal of the second switching sub-circuit, a first terminal electrically connected to a light-emitting element, and a second terminal electrically connected to a power source; the compensation sub-circuit has a first terminal electrically connected to the first terminal of the driving sub-circuit, and a second terminal electrically connected to the control terminal of the driving sub-circuit; the first switching sub-circuit has a control terminal electrically connected to a first signal input terminal, a first terminal electrically connected to the first terminal of the driving sub-circuit, and a second terminal electrically connected to an initial voltage input terminal; and the second switching sub-circuit has a control terminal electrically connected to a second signal input terminal, a first terminal electrically connected to the control terminal of the driving sub-circuit, and a second terminal electrically connected to a data signal input terminal.

公开(公告)号：US10593265B2

公开(公告)日：2020-03-17

申请号：US16080466

申请日：2018-01-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Quanhu Li ,  Song Meng

IPC: G09G3/3233 ,  G09G3/3225

Abstract: A compensation circuit and a manufacturing method thereof, a pixel circuit, a compensation device and a display device are disclosed. The OLED compensation circuit includes at least two sense transistors, the at least two sense transistors are in one-to-one correspondence with at least two sub-pixels in a pixel, and a first electrode of each of the sense transistors is electrically connected to a driving transistor of corresponding one of the sub-pixels; a magnitude relationship between channel width-to-length ratios of driving transistors of any two sub-pixels of the at least two sub-pixels is identical with a magnitude relationship between channel width-to-length ratios of two sense transistors corresponding to the two sub-pixels.

公开(公告)号：US20200082756A1

公开(公告)日：2020-03-12

申请号：US15748731

申请日：2017-06-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yi Cheng Lin ,  Quanhu Li ,  Cuili Gai ,  Ling Wang ,  Baoxia Zhang

IPC: G09G3/3258 ,  H01L27/32

Abstract: A display panel, a display device and a compensation method are provided. The display panel includes at least one pixel unit group, at least one sensing line, a plurality of gate lines, a plurality of first data lines and a plurality of second data lines. Each pixel unit group includes a plurality of pixel units arranged in two rows and a plurality of columns, the plurality of pixel units in each pixel unit group are connected to a same one of the gate lines, one of two pixel units in each column of each pixel unit group is connected to one of the first data lines corresponding thereto, other one is connected to one of the second data lines corresponding thereto, the plurality of pixel units in each pixel unit group are connected to a same sensing line.

公开(公告)号：US10546851B2

公开(公告)日：2020-01-28

申请号：US15509714

申请日：2016-09-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Pan Xu ,  Yongqian Li ,  Quanhu Li

IPC: H01L27/02 ,  G02F1/1362 ,  H01L27/12 ,  H01L29/788

Abstract: The present disclosure provides a substrate, including: a first line; a second line; a thin-film transistor (TFT) between the first line and the second line, having a floating gate structure, a source electrode electrically connected to the first line, and a drain electrode electrically connected to the second line; and a first point-discharge structure between the floating gate structure of the TFT and the first line.

公开(公告)号：US10546519B2

公开(公告)日：2020-01-28

申请号：US15565853

申请日：2017-03-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Ling Wang ,  Quanhu Li ,  Longyan Wang ,  Baoxia Zhang ,  Cuili Gai ,  Yicheng Lin

IPC: G11C19/00 ,  G09G3/20 ,  G09G3/36 ,  G09G3/3266 ,  G11C19/28

Abstract: The embodiments of the present disclosure disclose a gate driving circuit and a display panel. In the gate driving circuit, a control unit of a shift register may input a dual pulse control signal to a first control terminal of an output unit; and the output unit outputs a scanning signal having a pulse width equal to a pulse period of the dual pulse control signal to a corresponding gate line under the control of the dual pulse control signal. In this way, the output unit is controlled by the control unit to output a scanning signal of which a pulse width may be modulated, so as to output a gate signal of which a pulse width may be modulated.