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公开(公告)号：US11893928B2
公开(公告)日：2024-02-06
申请号：US17283174
申请日：2020-06-30
Inventor： Jing Yang , Chenyu Chen , Shuang Zhao , Zhongliu Yang , Wenbo Chen , Hongting Lu
IPC: G09G3/3233 , G09G3/325 , G09G3/3291 , H10K59/35 , H10K50/844 , H01L27/12 , G09G3/3225 , H10K59/131
CPC classification number: G09G3/3225 , H10K59/131 , G09G2300/0426 , G09G2300/0842 , G09G2310/061 , G09G2320/0233
Abstract: The embodiments of the present disclosure provide an array substrate and a related display panel and a related display device. An array substrate includes a plurality of pairs of scan signal lines. A first scan signal line of the m-th pair of scan signal lines is configured to provide a first scan signal to a sub-pixel in a (2n−1)-th column from sub-pixels in the m-th. And a plurality of pairs of driving reset control signal lines. A second driving reset control signal line of the m-th pair of driving reset control signal lines is configured to provide a second driving reset control signal to the sub-pixel in the 2n-th column from the sub-pixels in the m-th row. The m and n are integers greater than or equal to 1. In the embodiments of the present disclosure, the first scan signal line of the m-th pair of scan signal lines and the second driving reset control signal line of the m-th pair of driving reset control signal lines are the same signal line.
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公开(公告)号：US11232755B2
公开(公告)日：2022-01-25
申请号：US16976191
申请日：2019-10-23
Inventor： Zhongliu Yang , Yudan Shui , Yongfu Diao , Wenkang Wang , Chenyu Chen
IPC: G09G3/3275
Abstract: A display substrate and a manufacturing method therefor, and a display device are provided. The display substrate includes a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of data lead lines, at least one group of contact pads, and a first insulation layer. The base substrate includes a display region and a bonding region; the data lines are configured to provide data signals to the sub-pixels; the data lead lines are electrically connected to the data lines, respectively; the at least one group of contact pads includes a first group of contact pads and a second group of contact pads; the first insulation layer is in gaps between the contact pads and covers edges of the contact pads, and is configured to expose surfaces, away from the base substrate, of the contact pads.
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公开(公告)号：US12236884B2
公开(公告)日：2025-02-25
申请号：US18028458
申请日：2022-06-29
Inventor： Tianyi Cheng , Meng Li , Zhongliu Yang
IPC: G09G3/3258
Abstract: A pixel circuit, a driving method and a display device. The pixel circuit includes a light emitting element, a driving circuit, an energy storage circuit, an initialization circuit, and a compensation control circuit; the display period of the pixel circuit includes a refresh frame and a retention frame; the refresh frame and the retention frame respectively include a set phase and a light emitting phase set successively; the initialization circuit is configured to control provide the initial voltage to the first terminal and/or the second terminal of the driving circuit under the control of the initial control signal provided by the initial control terminal, in the refresh frame and the retention frame, at least in the set phase. The present disclose improves hysteresis and improves the display effect.
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公开(公告)号：US20240274613A1
公开(公告)日：2024-08-15
申请号：US18043304
申请日：2022-06-22
Inventor： Tiaomei Zhang , Haigang Qing , Gukhwan Song , Ziyang Yu , Yunsheng Xiao , Quanyong Gu , Mengqi Wang , Zhengkun Li , De Li , Hong Yi , Wenbo Chen , Zhongliu Yang , Shilong Wang , Pan Zhao
IPC: H01L27/12
CPC classification number: H01L27/124 , H01L27/1222
Abstract: An array substrate is provided. The array substrate includes a plurality of first reset signal lines configured to provide a plurality of first reset signals, a plurality of second reset signal lines configured to provide a plurality of second reset signals, a plurality of third reset signal lines, and a plurality of first connecting lines. A respective first reset signal line is connected to a row of first connecting lines, which in turn are connected to source electrodes of first reset transistors in a row of subpixels, respectively. The plurality of second reset signal lines and the plurality of third reset signal lines form an interconnected reset signal supply network. A respective second reset signal line is connected to one or more of the plurality of third reset signal lines. A respective third reset signal line is connected to one or more of the plurality of second reset signal lines.
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公开(公告)号：US12034014B2
公开(公告)日：2024-07-09
申请号：US17419812
申请日：2020-09-29
Inventor： Zhongliu Yang
CPC classification number: H01L27/1248 , H01L24/02 , H01L24/05 , H01L27/1288 , H01L27/124 , H01L2224/0221 , H01L2224/05073 , H01L2224/05553 , H01L2224/05559 , H01L2224/05573
Abstract: A display panel includes a base substrate, a bonding pattern, and a planarization layer pattern. The bonding pattern includes one or more conductive blocks. A bonding region is disposed on a surface, distal from the base substrate, of the conductive block. The planarization layer pattern is provided with an opening region and an occlusion region. An orthographic projection of the bonding region onto the base substrate is within an orthographic projection of the opening region onto the base substrate. The planarization layer pattern covers at least part of a side surface of the conductive block.
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Patent Agency Ranking
公开(公告)号：US20220077200A1
公开(公告)日：2022-03-10
申请号：US17419812
申请日：2020-09-29
Inventor： Zhongliu Yang
Abstract: A display panel includes a base substrate, a bonding pattern, and a planarization layer pattern. The bonding pattern includes one or more conductive blocks. A bonding region is disposed on a surface, distal from the base substrate, of the conductive block. The planarization layer pattern is provided with an opening region and an occlusion region. An orthographic projection of the bonding region onto the base substrate is within an orthographic projection of the opening region onto the base substrate. The planarization layer pattern covers at least part of a side surface of the conductive block.
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公开(公告)号：US12230214B2
公开(公告)日：2025-02-18
申请号：US17274665
申请日：2020-05-27
Inventor： Shuang Zhao , Chenyu Chen , Zhongliu Yang , Wenbo Chen , Zhuo Xu , Jing Yang , Hongting Lu
IPC: G09G3/3266 , G09G3/3275
Abstract: An array substrate, a display panel, and a driving method of the array substrate are provided. The array substrate includes: a plurality of pairs of gate lines, each pair including a first gate line and a second gate line, and a pixel array, including pixel units arranged into a plurality of rows and a plurality of columns. A scan signal terminal of a pixel unit of an nth column in an mth row of pixel units is connected to the first gate line in an mth pair of gate lines to receive a first scan signal; m and n are positive integers; a reset signal terminal of the pixel unit of the (n+1)th column in the mth row of pixel units is connected to the first gate line in the mth pair of gate lines to receive the first scan signal serving as a first reset signal.
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公开(公告)号：US20250015094A1
公开(公告)日：2025-01-09
申请号：US18548497
申请日：2022-11-29
Inventor： Bo Zhang , Zhongliu Yang , Tianyi Cheng , Benlian Wang
IPC: H01L27/12 , G09G3/3233
Abstract: An array substrate is provided. The array substrate includes a plurality of pixel driving circuits. A respective pixel driving circuit of the plurality of pixel driving circuit includes a driving transistor, a compensating transistor, and a first reset transistor. An active layer of the driving transistor is in a first semiconductor material layer. Active layers of the compensating transistor and the first reset transistor are in a second semiconductor material layer different from the first semiconductor material layer. The array substrate includes a third connecting line in a first signal line layer, and connected to a second electrode of the compensating transistor. The third connecting line crosses over at least two control signal lines.
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公开(公告)号：US20240363079A1
公开(公告)日：2024-10-31
申请号：US18028830
申请日：2022-04-22
Inventor： Zhengkun Li , De Li , Haigang Qing , Yue Long , Cong Liu , Qiwei Wang , Binyan Wang , Zhongliu Yang , Tianyi Cheng , Ni Yang , Qiyang Wu
IPC: G09G3/3275 , G09G3/32
CPC classification number: G09G3/3275 , G09G3/32 , G09G2300/0426 , G09G2310/0275 , G09G2310/08 , G09G2320/0233
Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.
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公开(公告)号：US11915643B2
公开(公告)日：2024-02-27
申请号：US17267261
申请日：2020-05-06
Inventor： Hongting Lu , Yuhsiung Feng , Xin Mou , Chenyu Chen , Shuang Zhao , Zhongliu Yang , Jing Yang , Wenbo Chen
IPC: G09G3/3233 , H10K59/131
CPC classification number: G09G3/3233 , H10K59/1315 , G09G2300/0408 , G09G2300/0426 , G09G2300/0452 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0272 , G09G2310/08 , G09G2320/043 , G09G2330/026
Abstract: A display substrate and a drive method thereof and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a light-emitting element in response to a first reset control voltage to reversely bias the light-emitting element.
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