公开(公告)号：US20080068883A1

公开(公告)日：2008-03-20

申请号：US11651521

申请日：2007-01-10

Applicant: Sang-Gu Kang ,  Young-Ho Lim

Inventor： Sang-Gu Kang ,  Young-Ho Lim

IPC: G11C16/04

CPC classification number: G11C11/5628

Abstract: Flash memory devices and methods of programming the same are provided. The flash memory devices include a plurality of memory cells storing multi-bit data representing at least one of first through fourth states and including most significant bits and least significant bits. The method includes programming the plural memory cells into a provisional state according to the least significant bit, and programming the plurality of memory cells into the second through fourth states from the first and provisional states according to the most significant bit. Programming the plurality of memory cells into the second through fourth states includes simultaneously programming the plurality of memory cells at least partially into at least two states during one programming operation period.

Abstract translation: 提供闪存设备及其编程方法。 闪速存储器件包括存储多位数据的多个存储单元，该多位数据表示第一至第四状态中的至少一个，并且包括最高有效位和最低有效位。 该方法包括根据最低有效位将多个存储器单元编程为临时状态，并根据最高有效位将第一至暂态状态的多个存储单元编程为第二至第四状态。 将多个存储器单元编程为第二至第四状态包括在一个编程操作周期期间至少部分地将多个存储器单元编程为至少两个状态。

公开(公告)号：US20080037331A1

公开(公告)日：2008-02-14

申请号：US11871297

申请日：2007-10-12

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C16/06

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract translation: 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US20080025098A1

公开(公告)日：2008-01-31

申请号：US11776729

申请日：2007-07-12

Applicant: Dae-Seok BYEON ,  Young-ho LIM

Inventor： Dae-Seok BYEON ,  Young-ho LIM

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3427

Abstract: A method of programming a nonvolatile memory device using hybrid local boosting which includes a plurality of cell strings each having a plurality of electrically erasable and programmable memory cells connected in series and a plurality of wordlines respectively connected to control gates of the plurality of memory cells. The address of a selected cell that is to be programmed is received. A determination is made as to whether a selected wordline connected to the selected cell is located above or under a reference wordline based on the received address. The selected cell is programmed using local boosting when the selected wordline corresponds to the reference wordline or is located above the reference wordline. The selected cell is programmed using self-boosting when the selected wordline is located under the reference wordline. The programming method reduces circuit size of a nonvolatile memory device employing the programming method and efficiently prevents program disturbance due to charge sharing.

Abstract translation: 一种使用混合局部升压来编程非易失性存储器件的方法，该方法包括多个单元串，每个单元串具有分别连接到多个存储器单元的控制栅极的多个电可擦除可编程存储器单元和多个字线。 接收要编程的所选单元的地址。 确定连接到所选择的单元的所选择的字线是否位于参考字线的上方或下方，基于所接收的地址。 当所选择的字线对应于参考字线或位于参考字线上方时，使用本地升压来编程所选单元格。 当所选择的字线位于参考字线下方时，使用自增强来对所选择的单元进行编程。 编程方法减少了使用编程方法的非易失性存储器件的电路尺寸，并且有效地防止了由于电荷共享引起的程序干扰。

公开(公告)号：US20070171722A1

公开(公告)日：2007-07-26

申请号：US11595925

申请日：2006-11-13

Applicant: Sang-gu Kang ,  Young-Ho Lim

Inventor： Sang-gu Kang ,  Young-Ho Lim

IPC: G06F12/00 ,  G11C16/04 ,  G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

Abstract: A memory system includes a flash memory and a memory controller configured to control the flash memory. The memory controller determines whether program data provided from a host are all stored in the flash memory during a program operation. When the determination result is that the program data are all stored in the flash memory, the memory controller controls the flash memory to execute a dummy program operation for the next wordline of a final wordline in which the program data are stored.

Abstract translation: 存储器系统包括闪速存储器和被配置为控制闪速存储器的存储器控​​制器。 存储器控制器在程序操作期间确定从主机提供的程序数据是否全部存储在闪速存储器中。 当确定结果是程序数据全部存储在闪速存储器中时，存储器控制器控制闪存以对存储程序数据的最终字线的下一个字线执行虚拟程序操作。

公开(公告)号：US20070171709A1

公开(公告)日：2007-07-26

申请号：US11598090

申请日：2006-11-13

Applicant: Sang-gu Kang ,  Young-Ho Lim

Inventor： Sang-gu Kang ,  Young-Ho Lim

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3459

Abstract: The invention provides a programming method for a flash memory device including first and second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method may include programming memory cells, connected with a selected row and the second bitlines, with multi-bit data; determining whether the selected row is the last row; and reprogramming programmed memory cells connected with the selected row being the last row and the first bitlines when the determination result is that the selected row is the last row.

Abstract translation: 本发明提供了一种用于闪存器件的编程方法，其包括与多个存储器单元连接的第一和第二位线，用于存储指示多个状态之一的多位数据。 程序方法可以包括利用多位数据来编程与所选择的行和第二位线连接的存储器单元; 确定所选行是否是最后一行; 并且当确定结果是所选择的行是最后一行时，与所选行连接的编程存储器单元重新编程为最后一行和第一位。

公开(公告)号：US20060268654A1

公开(公告)日：2006-11-30

申请号：US11416064

申请日：2006-05-03

Applicant: Dong Hyuk Chae ,  Young Ho Lim

Inventor： Dong Hyuk Chae ,  Young Ho Lim

IPC: G11C8/00

CPC classification number: G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/5642

Abstract: A nonvolatile semiconductor memory device is provided which includes a memory array, a page buffer, and a row decoder. The memory array includes a plurality of nonvolatile memory cells, a bit line, and a word line, and the row decoder driven to control the word line of the memory array. The page buffer is electrically connected to the bit line and includes a main data latch and a sub-data latch. The page buffer, which is configured such that flipping of the main data latch is inhibited according to a logic state of the sub-data latch, further includes a main latch block, a sub-latch block, and a latch control block. The main latch block drives the main data latch and maps a logic state of the main data latch to a threshold voltage of a corresponding memory cell through the bit line. The sub-latch block drives the sub-data latch, where the sub-data latch is flipped depending on the voltage level of the bit line. The latch control block selectively flips the main data latch depending on the voltage level of the bit line, where the latch control block is disabled depending on a logic state of the sub-data latch.

公开(公告)号：US06678191B2

公开(公告)日：2004-01-13

申请号：US10165838

申请日：2002-06-06

Applicant: Seung-Jae Lee ,  Young-Ho Lim

Inventor： Seung-Jae Lee ,  Young-Ho Lim

IPC: G11C1604

CPC classification number: G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/002

Abstract: Disclosed is a nonvolatile semiconductor memory device having a memory cell array by which random access can be performed. The memory cell array structure of the nonvolatile semiconductor memory device having a main memory cell array formed of a plurality of NAND cell strings includes a sub memory cell array having a plurality of NAND cell strings that is provided therein with memory cell transistors. The number of the memory cell transistors in the sub memory cell array is less than that of the memory cell transistors in the NAND cell strings of the main memory cell arrays. The sub memory cell array is operationally connected to main bit lines of the main memory cell array during program and erase operations and is electrically disconnected with the main bit lines during read operation, thereby having a separate read path that is independent from the read path of the main memory cell array.

Abstract translation: 公开了一种具有可以进行随机存取的存储单元阵列的非易失性半导体存储器件。 具有由多个NAND单元串构成的主存储单元阵列的非易失性半导体存储器件的存储单元阵列结构包括具有在其中设置有存储单元晶体管的多个NAND单元串的副存储单元阵列。 子存储单元阵列中的存储单元晶体管的数量小于主存储单元阵列的NAND单元串中的存储单元晶体管的数量。 子存储单元阵列在编程和擦除操作期间可操作地连接到主存储单元阵列的主位线，并且在读取操作期间与主位线电连接，从而具有独立于读取路径的读取路径 主存储单元阵列。

公开(公告)号：US06590442B2

公开(公告)日：2003-07-08

申请号：US09877811

申请日：2001-10-11

Applicant: Dae-Seok Byeon ,  Young-Ho Lim

Inventor： Dae-Seok Byeon ,  Young-Ho Lim

IPC: G05F324

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A voltage boosting circuit for an integrated circuit includes a booster and a voltage clamp circuit. The booster generates a boosted voltage higher than the supply voltage in response to a boosting control signal. The voltage clamp circuit includes a voltage detector, a pulse generator, and a discharge circuit. The voltage detector generates, in response to the boosting control signal, a detected voltage signal representing an attribute of the boosted voltage. The pulse generator generates a pulse signal responsive to the detected voltage signal. And the discharge circuit discharges the boosted voltage during an activation period of the pulse signal. This largely stabilizes the output voltage of the booster.

公开(公告)号：US06542406B2

公开(公告)日：2003-04-01

申请号：US09905612

申请日：2001-07-13

Applicant: Dae-Seok Byeon ,  Myung-Jae Kim ,  Young-Ho Lim ,  Seung-Keun Lee

Inventor： Dae-Seok Byeon ,  Myung-Jae Kim ,  Young-Ho Lim ,  Seung-Keun Lee

IPC: G11C1604

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C16/08

Abstract: A nonvolatile semiconductor memory device includes a plurality of first wordlines, a plurality of second wordlines coupled to memory cells, the second wordlines being assigned to each of memory sectors, a plurality of transistors each of which connects a first wordline to a second wordline, and a circuit for controlling the transistors in common. One of the first wordlines is connected to one of the second wordlines through one of the transistors. A circuit area for decoding is reduced and current consumption is minimized.

公开(公告)号：US06529413B2

公开(公告)日：2003-03-04

申请号：US09952807

申请日：2001-09-13

Applicant: June Lee ,  Young-Ho Lim

Inventor： June Lee ,  Young-Ho Lim

IPC: G11C1606

CPC classification number: G11C16/3477 ,  G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: Disclosed herein is an erase method of a flash memory device that comprises discrete first and second erase discrimination periods. An erase operation is carried out using a bulk stepping scheme during the first erase discrimination period while the erase operation is carried out using a fixed bulk voltage during the second erase discrimination period. According to this method, the number of over-erased memory cells caused by the bad erase property is reduced, so that a total erase time of the flash memory device can be reduced and over-erase can be prevented.