公开(公告)号：US07626869B2

公开(公告)日：2009-12-01

申请号：US11745327

申请日：2007-05-07

Applicant: Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

Inventor： Xuguang Wang ,  Yi He ,  Zhizheng Liu ,  Sung-Yong Chung ,  Darlene G. Hamilton ,  Ashot Melik-Martirosian ,  Gulzar Kathawala ,  Ming Sang Kwan ,  Mark Randolph ,  Timothy Thurgate

IPC: G11C11/34

CPC classification number: G11C16/16

Abstract: Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.

Abstract translation: 同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。 然而，其他字线不受影响，因为它们在联系人旁边。 因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

公开(公告)号：US20090239952A1

公开(公告)日：2009-09-24

申请号：US12465980

申请日：2009-05-14

Applicant: Roman PEREZ-SOLER ,  Yi-He LING

Inventor： Roman PEREZ-SOLER ,  Yi-He LING

IPC: A61K31/122 ,  A61P17/00

CPC classification number: A61K31/122 ,  A61K31/53

Abstract: The invention provides methods and compositions tor treating and preventing a skin rash secondary to anti-epidermal growth factor receptor (BGKR) therapy, where the method comprises applying a vitamin K analog or a phosphatase inhibitor to the skin.

Abstract translation: 本发明提供治疗和预防继发于抗表皮生长因子受体（BGKR）治疗的皮肤疹的方法和组合物，其中该方法包括向皮肤施用维生素K类似物或磷酸酶抑制剂。

公开(公告)号：US07561471B2

公开(公告)日：2009-07-14

申请号：US11724711

申请日：2007-03-16

Applicant: Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

Inventor： Sheung-Hee Park ,  Xuguang Wang ,  Wing Leung ,  Ming-Sang Kwan ,  Yi He ,  Edward Franklin Runnion

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/14

Abstract: Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.

Abstract translation: 提供了擦除闪存单元的方法，其提高了擦除循环速度和可靠性。 一个实施例包括将阶梯式或倾斜的漏极电压图案交互地施加到存储器单元的漏极，以及脉冲栅极电压图案到达预定数量的栅极脉冲的存储器单元的栅极，或者直到所有存储器单元被擦除。 在另一个实施例中，提供擦除偏置电路用于擦除闪速存储器单元的扇区，该电路包括分别选择字线行和单元列的行和列解码器，该电源偏置装置为 以及图案化脉冲偏压装置，其被配置为向由行解码器选择的单元的栅极和漏极电压图案提供脉冲栅极电压图案到由列解码器选择的单元的漏极。

公开(公告)号：US20090150478A1

公开(公告)日：2009-06-11

申请号：US11952838

申请日：2007-12-07

Applicant: Jichuan Xu ,  Yi He

Inventor： Jichuan Xu ,  Yi He

IPC: G06F15/16

CPC classification number: G06Q10/10

Abstract: A data transferring system and an object tracking system. The data transferring method includes generating messages based on the data, connecting the clients to the server, generating a plurality of event trigger thread instances, each of the instances being in communication with a corresponding one of the clients and sending the messages from the server to the clients through remote events by using the corresponding event trigger thread instance to control the communication between the server and the client.

Abstract translation: 数据传输系统和对象跟踪系统。 数据传输方法包括基于数据生成消息，将客户端连接到服务器，生成多个事件触发线程实例，每个实例与相应的客户端通信，并将消息从服​​务器发送到 客户端通过远程事件通过使用相应的事件触发线程实例来控制服务器与客户端之间的通信。

公开(公告)号：USD564085S1

公开(公告)日：2008-03-11

申请号：US29249307

申请日：2006-09-29

Applicant: Yi-He Huang

Designer： Yi-He Huang

公开(公告)号：US07319615B1

公开(公告)日：2008-01-15

申请号：US11497597

申请日：2006-08-02

Applicant: Sheung-Hee Park ,  Gwyn Jones ,  Wing Leung ,  Edward Franklin Runnion ,  Ming-Sang Kwan ,  Xuguang Wang ,  Yi He

Inventor： Sheung-Hee Park ,  Gwyn Jones ,  Wing Leung ,  Edward Franklin Runnion ,  Ming-Sang Kwan ,  Xuguang Wang ,  Yi He

IPC: G11C16/06

CPC classification number: G11C16/344 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3445

Abstract: A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

Abstract translation: 一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。 当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

公开(公告)号：US20070277958A1

公开(公告)日：2007-12-06

申请号：US11421546

申请日：2006-06-01

Applicant: Yi-He Huang

Inventor： Yi-He Huang

IPC: H05K7/20

CPC classification number: H01L23/467 ,  H01L23/427 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat dissipator for mounting on a heat-generating element includes a heat-dissipating body, a fan assembly, a bottom stand and a top stand. The heat-dissipating body is formed into a spherical body and constituted of a plurality of heat-dissipating pieces. The heat-dissipating body is provided with a sealed accommodating space therein for accommodating the fan assembly. Further, the bottom stand and the top stand are provided at the upper and lower ends of the heat-dissipating body, respectively. Further, the bottom of the fan assembly has a connecting seat for connecting to the bottom stand to fix the fan assembly. Finally, the bottom stand is provided with a heat-conducting block for adhering to the heat-generating element, thereby to conduct the heat generated by the operation of the heat-generating element to the heat-dissipating body. In this way, the heat can be uniformly dissipated to each heat-dissipating piece. With the airflow generated by the fan assembly, the heat-dissipating effect can be satisfactorily achieved.

Abstract translation: 用于安装在发热元件上的散热器包括散热体，风扇组件，底架和顶架。 散热体形成为由多个散热片构成的球体。 散热体在其中设置有用于容纳风扇组件的密封容纳空间。 此外，底座和顶架分别设置在散热体的上端和下端。 此外，风扇组件的底部具有用于连接到底架的连接座，以固定风扇组件。 最后，底架设置有用于粘附到发热元件的导热块，从而将由发热元件的操作产生的热量传导到散热体。 以这种方式，可以将热量均匀地散发到每个散热片上。 随着风扇组件产生的气流，可​​以令人满意地实现散热效果。

公开(公告)号：US07285827B1

公开(公告)日：2007-10-23

申请号：US11194449

申请日：2005-08-02

Applicant: Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

Inventor： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L27/0255

Abstract: A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

Abstract translation: 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。

公开(公告)号：US07269067B2

公开(公告)日：2007-09-11

申请号：US11174560

申请日：2005-07-06

Applicant: Shankar Sinha ,  Zhizheng Liu ,  Yi He

Inventor： Shankar Sinha ,  Zhizheng Liu ,  Yi He

IPC: G11C11/34

CPC classification number: H01L29/7923 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

Abstract: A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.

Abstract translation: 一种对非易失性存储器件中的存储器单元进行编程的方法包括：将第一电压施加到与存储器单元相关联的控制栅极，并将第二电压施加到与存储器单元相关联的漏极区域。 该方法还包括向与存储器单元相关联的源极区域施加正偏压和/或将负偏压施加到与存储器单元相关联的衬底区域。

公开(公告)号：US06795357B1

公开(公告)日：2004-09-21

申请号：US10283590

申请日：2002-10-30

Applicant: Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

Inventor： Zhizheng Liu ,  Yi He ,  Mark W. Randolph ,  Sameer S. Haddad

IPC: G11C700

CPC classification number: G11C16/0491 ,  G11C16/0475 ,  G11C16/26

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.

Abstract translation: 检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加 到与沟道区形成漏极结的第二位线的漏极电压。 源极电压可以是小的正电压，并且漏极电压可能大于源极电压。 将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。 偏置电压可以是负电压。