公开(公告)号：US08301788B2

公开(公告)日：2012-10-30

申请号：US11220899

申请日：2005-09-07

Applicant: Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

Inventor： Gregg A. Bouchard ,  David A. Carlson ,  Richard E. Kessler ,  Muhammad R. Hussain

IPC: G06F15/16 ,  G06F15/173 ,  H04L12/28 ,  H04J3/06

CPC classification number: G06F9/30003 ,  H04L1/0045

Abstract: A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

Abstract translation: 描述了一种用于遍历确定性有限自动机（DFA）图的计算机可读指令，以便在即将进行的分组数据中实时地执行模式搜索。 该指令包括一个或多个预定义字段。 其中一个字段包括用于标识几个先前存储的DFA图形之一的DFA图形标识符。 另一个领域包括用于使用所识别的DFA图形来识别要处理的输入数据的输入参考。 另一个领域包括用于存储响应于经处理的输入数据生成的结果的输出参考。 这些指令被转发到适用于使用识别的DFA图处理输入数据的DFA引擎，并根据输出参考的指示提供结果。

公开(公告)号：US07535907B2

公开(公告)日：2009-05-19

申请号：US11218727

申请日：2005-09-02

Applicant: Muhammad R. Hussain ,  Imran Badr ,  Faisal Masood ,  Philip H. Dickinson ,  Richard E. Kessler ,  Daniel A. Katz ,  Michael S. Bertone ,  Robert A. Sanzone ,  Thomas F. Hummel ,  Gregg A. Bouchard

Inventor： Muhammad R. Hussain ,  Imran Badr ,  Faisal Masood ,  Philip H. Dickinson ,  Richard E. Kessler ,  Daniel A. Katz ,  Michael S. Bertone ,  Robert A. Sanzone ,  Thomas F. Hummel ,  Gregg A. Bouchard

IPC: H04L12/28 ,  H04L12/56 ,  G06F15/16

CPC classification number: H04L69/16 ,  H04L49/90 ,  H04L49/9047 ,  H04L69/163

Abstract: A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

Abstract translation: 网络传输层加速器加速数据包的处理，使数据包能够以线速转发。 为了加速分组的处理，加速器在封装在用于连接的分组中的网络传输层报头上执行预处理，并且在发送分组之前执行在线网络传输层校验和插入。 加速器中的定时器单元调度接收到的分组的处理。 加速器还包括一个空闲池分配器，用于管理用于存储接收到的分组的缓冲器，以及分组顺序单元，用于同步用于相同连接的接收分组的处理。

公开(公告)号：US06944731B2

公开(公告)日：2005-09-13

申请号：US10025331

申请日：2001-12-19

Applicant: Gregg A. Bouchard ,  Mauricio Calle ,  Ravi Ramaswami

Inventor： Gregg A. Bouchard ,  Mauricio Calle ,  Ravi Ramaswami

IPC: G06F12/06 ,  G06F13/16 ,  G11C7/00 ,  G06F12/00

CPC classification number: G06F13/1647 ,  Y02D10/14

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence.

Abstract translation: 具有多个存储体的存储器系统被配置为防止存取请求之间的存储体冲突。 存储器系统包括存储器控制器和可操作地耦合到存储器控制器的多个存储器组，其中每个存储器组被配置用于存储多个数据项。 更具体地，给定数据项被存储为数据项的多个副本，其中多个副本被存储在指定的最小数量的存储体的相应的一个中。 存储器控制器适于根据指定的存储体访问顺序处理存储在存储体中的数据项的访问请求。