公开(公告)号：US5764952A

公开(公告)日：1998-06-09

申请号：US450456

申请日：1995-05-25

申请人： John P. Hill

发明人： John P. Hill

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/273 ,  G11C29/32 ,  G01R31/28 ,  G06F3/00

CPC分类号： G06F11/2221 ,  G01R31/318572 ,  G06F11/2733 ,  G11C29/32

摘要： A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in the two-wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.

摘要翻译： 集成电路中的两线专用诊断数据端口为集成电路的所有内部功能提供可见性。 将内部信号或信号写入专用诊断数据端口中的串行存储器。 串行连接的存储器连接到专用诊断数据端口的两线输出端口。 双线输出端口中的第一根导线是数据线，二线输出端口中的第二根导线是时钟导线。 将存储的信息从串行连接的存储器传送到两线输出端口是通过写入专用诊断数据端口中的控制寄存器来启动的。 响应于向控制寄存器的写入，到专用诊断数据端口的时钟输入线上的时钟信号被耦合到第二线，并且用于将存储的信息从串行连接的存储器顺序地移位到数据线。 来自集成电路的两线上的信号由集成电路外部的移位/锁存控制电路处理。 在时钟线上的时钟信号终止之后的预定时间，即在预定时间段内保持不活动，移位/锁存控制电路产生可用于捕获通过数据线发送的数据的锁存信号。

公开(公告)号：US5761129A

公开(公告)日：1998-06-02

申请号：US824202

申请日：1997-03-25

申请人： David Glen Roe ,  Richard Lingard Kalish

发明人： David Glen Roe ,  Richard Lingard Kalish

IPC分类号： G06F13/16 ,  G11C13/00

CPC分类号： G06F13/161

摘要： A RAM and I/O controller is provided with logic for controlling access to a DRAM and to one or more input and/or output latches, each of which are coupled to a RAM data bus. The logic receives input signals such as a refresh request signal and a RAM access request signal from other circuits or devices, and outputs one or more associated control signals onto a RAM control bus, such as a RAS output signal or a CAS output signal. The logic includes at least one idle state during which the DRAM is in a RAS or CAS precharge period. During the idle state, the logic de-asserts the RAS or CAS output and asserts one or more control signals to the input and/or output latches so as to perform at least one write and/or read operation of miscellaneous data signals with the latches 112 and 114 of FIG. 2a over the temporarily idle RAM data bus. A method is also provided for I/O multiplexing a RAM bus by providing one or more control signals, such as a RAS signal and a CAS signal for a DRAM on a RAM control bus, and performing at least one read operation and/or write operation on a RAM data bus from circuits or devices, other than the DRAM, during one or more of the RAM's precharge cycles or periods.

摘要翻译： RAM和I / O控制器被提供有用于控制对DRAM以及一个或多个输入和/或输出锁存器的访问的逻辑，每个锁存器被耦合到RAM数据总线。 逻辑从其他电路或设备接收诸如刷新请求信号和RAM访问请求信号的输入信号，并将一个或多个相关控制信号输出到诸如RAS输出信号或CAS输出信号的RAM控制总线上。 该逻辑包括至少一个空闲状态，在该状态期间，DRAM处于RAS或CAS预充电期间。 在空闲状态期间，逻辑取消断言RAS或CAS输出，并将一个或多个控制信号置于输入和/或输出锁存器中，以便对锁存器执行杂项数据信号的至少一次写和/或读操作 112和114。 2a在暂时空闲的RAM数据总线上。 还提供了一种用于通过在RAM控制总线上提供用于DRAM的RAS信号和CAS信号的一个或多个控制信号并且执行至少一个读取操作和/或写入来对RAM总线进行I / O多路复用的方法 在RAM的预充电周期或周期期间的一个或多个期间，在来自DRAM之外的电路或器件的RAM数据总线上进行操作。

公开(公告)号：US5684972A

公开(公告)日：1997-11-04

申请号：US294234

申请日：1994-08-22

申请人： John P. Hill ,  David L. Dyer ,  Nicolas C. Assoud

发明人： John P. Hill ,  David L. Dyer ,  Nicolas C. Assoud

IPC分类号： G11B5/596 ,  G06F13/00 ,  G05B19/29

CPC分类号： G11B5/59605 ,  G11B5/59688

摘要： An integrated circuit includes a programmable servo burst sequencer that includes an instruction memory, an instruction register, and an address control circuit. The instruction register drives a plurality of output lines of the programmable servo burst sequencer. The programmable servo burst sequencer can process a plurality of fields in any one of a plurality of servo sectors. The programmable servo burst sequencer eliminates the need for a specific servo burst sequencer for each possible configuration of the plurality of fields in a servo sector. The user simply uses a plurality of instructions to configure the programmable servo burst sequencer so that the programmed servo burst sequencer can process the plurality of fields in the servo sector information on the user's disk drive.

摘要翻译： 集成电路包括可编程伺服脉冲序列发生器，其包括指令存储器，指令寄存器和地址控制电路。 指令寄存器驱动可编程伺服脉冲序列发生器的多条输出线。 可编程伺服脉冲序列发生器可以处理多个伺服扇区中的任何一个中的多个场。 可编程伺服脉冲序列发生器消除了对伺服扇区中的多个场的每个可能配置的特定伺服脉冲序列发生器的需要。 用户简单地使用多个指令来配置可编程伺服脉冲序列发生器，使得编程的伺服脉冲序列发生器可以处理用户磁盘驱动器上的伺服扇区信息中的多个场。

公开(公告)号：US5592348A

公开(公告)日：1997-01-07

申请号：US145037

申请日：1993-10-28

申请人： Clifford E. Strang, Jr.

发明人： Clifford E. Strang, Jr.

IPC分类号： G06F3/06 ,  G11B5/55 ,  G11B5/596 ,  G11B19/02 ,  G11B19/04 ,  G11B19/12 ,  G11B20/10 ,  G11B27/30

CPC分类号： G06F3/0601 ,  G11B19/02 ,  G11B19/04 ,  G11B19/12 ,  G11B20/10 ,  G11B27/3027 ,  G11B5/5526 ,  G11B5/553 ,  G11B5/5534 ,  G11B5/59633 ,  G11B5/59644 ,  G06F2003/0692 ,  G11B2220/20

摘要： A novel disk controller and method performed by a disk controller is disclosed which provides a highly efficient means of interrupting the reading or writing of a field in a sector on a magnetic disk, for skipping over a servo burst located anywhere within the field. The servo burst may be located at a different location in the fields of successive sectors. In the preferred embodiment, the servo burst skipping operation is controlled by microcode in the disk controller's sequencer RAM, and the servo burst skipping operation is initiated by a servo interrupt signal. The servo interrupt signal is generated by the disk controller when a servo burst is about to occur. This servo interrupt signal may be generated at fixed time intervals, using a count from a disk clock, or by counting the bytes in a sector leading to the servo burst. The number of bytes leading to the servo burst may vary, and, in one embodiment, the number of bytes before the servo burst occurs within a sector is contained in the ID field for that sector. The servo burst skipping operation performs the steps necessary for skipping over the servo burst and causing the microcode to return to an appropriate instruction in the microcode.

摘要翻译： 公开了一种由磁盘控制器执行的新颖的磁盘控制器和方法，该磁盘控制器和方法提供了一种高效的方法来中断在磁盘上的扇区中的磁场的读取或写入，用于跳过位于磁场内任何位置的伺服脉冲。 伺服脉冲串可以位于连续扇区的不同位置。 在优选实施例中，伺服突发跳过操作由盘控制器的定序器RAM中的微码来控制，伺服突发跳过操作由伺服中断信号启动。 当伺服脉冲串即将发生时，伺服中断信号由磁盘控制器产生。 可以使用来自磁盘时钟的计数，或通过对导致伺服脉冲串的扇区中的字节进行计数，以固定的时间间隔生成该伺服中断信号。 导致伺服脉冲串的字节数可以变化，并且在一个实施例中，扇区内发生伺服突发之前的字节数被包含在该扇区的ID字段中。 伺服突发跳过操作执行跳过伺服脉冲串所必需的步骤，并使微代码返回到微代码中的适当指令。

公开(公告)号：US5551054A

公开(公告)日：1996-08-27

申请号：US795161

申请日：1991-11-19

申请人： John S. Packer

发明人： John S. Packer

IPC分类号： G06F3/06 ,  G06F13/28 ,  G11B20/10 ,  G11C7/00 ,  G06F12/00

CPC分类号： G06F3/0601 ,  G06F13/28 ,  G06F2003/0691

摘要： According to the principles of this invention, a disk drive includes a page mode buffer memory controller that is used to control transfer of data from and to a buffer memory. The page mode buffer memory controller transfers a page of Nb data bytes from the buffer memory to a host of the disk drive if the data transfer is not interrupted by another request to the page mode buffer memory controller. The transfer of Nb data bytes requires only four overhead clock cycles. The page mode buffer memory controller includes a buffer prioritizer, a memory sequencer, a disk FIFO circuit, a refresh counter, a buffer address generator, and a disk byte counter. The buffer prioritizer receives request signals on port input lines and generates control output signals to the memory sequencer, disk byte counter and buffer address generator. The refresh counter repetitively loads itself with a refresh time period, that is stored in a register, for refreshing the buffer memory. After the refresh counter is loaded, the counter counts down and generates a refresh request at the end of each refresh time period. The memory sequencer includes a state machine that generates control signals for the buffer memory as well as control signals for the buffer address generator and disk byte counter. The buffer address generator generates the addresses for the locating in the buffer memory that are used in the data transfer.

摘要翻译： 根据本发明的原理，磁盘驱动器包括页面模式缓冲存储器控制器，其用于控制​​从缓冲存储器传送数据到缓冲存储器。 页面模式缓冲存储器控制器将数据字节从缓冲存储器传送到磁盘驱动器的主机，如果数据传输不被页模式缓冲存储器控制器的另一请求中断。 Nb数据字节的传输只需要四个开销时钟周期。 页面模式缓冲存储器控制器包括缓冲区分配器，存储序列器，盘FIFO电路，刷新计数器，缓冲器地址生成器和盘字节计数器。 缓冲区分配器在端口输入线上接收请求信号，并产生控制输出信号到存储器定序器，磁盘字节计数器和缓冲地址发生器。 刷新计数器重新加载自身，具有存储在寄存器中的刷新时间段，用于刷新缓冲存储器。 刷新计数器加载后，计数器倒计时，并在每个刷新时间段结束时生成刷新请求。 存储器定序器包括一个状态机，其产生用于缓冲存储器的控制信号以及缓冲器地址发生器和盘字节计数器的控制信号。 缓冲地址生成器生成用于在数据传输中使用的缓冲存储器中的定位的地址。

公开(公告)号：US5544107A

公开(公告)日：1996-08-06

申请号：US294127

申请日：1994-08-22

申请人： John P. Hill

发明人： John P. Hill

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/273 ,  G11C29/32 ,  H03K19/177 ,  G06F11/26

CPC分类号： G06F11/2221 ,  G01R31/318572 ,  G06F11/2733 ,  G11C29/32

摘要： A two-wire dedicated diagnostic data port in an integrated circuit provides visibility for all internal functions of the integrated circuit. An internal signal or signals are written to a serially connected memory in the dedicated diagnostic data port. The serially connected memory is connected to a two-wire output port of the dedicated diagnostic data port. A first wire in the two-wire output port is a data wire and a second wire in said the wire output port is a clock wire. Transfer of the stored information from the serially connected memory to the two-wire output port is initiated by writing to a control register in the dedicated diagnostic data port. In response to writing to the control register, a clock signal on a clock input line to the dedicated diagnostic data port is coupled to the second wire, and is used to serially shift the stored information from the serially connected memory to the data wire. The signals on the two-wires from the integrated circuit are processed by a shift/latch control circuit that is external to the integrated circuit. A predetermined time after the clock signal on the clock wire terminates, i.e., remains inactive for a predetermined period, the shift/latch control circuit generates a latch signal that can be used to capture the data transmitted over the data wire.

摘要翻译： 集成电路中的两线专用诊断数据端口为集成电路的所有内部功能提供可见性。 将内部信号或信号写入专用诊断数据端口中的串行存储器。 串行连接的存储器连接到专用诊断数据端口的两线输出端口。 双线输出端口中的第一线是数据线，并且所述线输出端口中的第二线是时钟线。 将存储的信息从串行连接的存储器传送到两线输出端口是通过写入专用诊断数据端口中的控制寄存器来启动的。 响应于向控制寄存器的写入，到专用诊断数据端口的时钟输入线上的时钟信号被耦合到第二线，并且用于将存储的信息从串行连接的存储器顺序地移位到数据线。 来自集成电路的两线上的信号由集成电路外部的移位/锁存控制电路处理。 在时钟线上的时钟信号终止之后的预定时间，即在预定时间段内保持不活动，移位/锁存控制电路产生可用于捕获通过数据线发送的数据的锁存信号。

公开(公告)号：US20120210058A1

公开(公告)日：2012-08-16

申请号：US13455058

申请日：2012-04-24

申请人： Steffen Mittendorff ,  Dieter Massa

发明人： Steffen Mittendorff ,  Dieter Massa

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0866 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0897 ,  G06F2212/222 ,  G06F2212/313 ,  G06F2212/462

摘要： Methods, systems, and computer programs for managing storage using a solid state drive (SSD) read cache memory are presented. One method includes an operation for determining whether data corresponding to a read request is available in a SSD memory when the read request causes a miss in a memory cache. The read request is served from the SSD memory when the data is available in the SSD memory, and when the data is not available in the SSD memory, SSD memory tracking logic is invoked and the read request is served from a hard disk drive. Invoking the SSD memory tracking logic includes determining whether a fetch criteria for the data has been met, and loading the data corresponding to the read request in the SSD memory when the fetch criteria has been met. The use of the SSD as a read cache improves memory performance for random data reads.

摘要翻译： 提出了使用固态驱动器（SSD）读取高速缓冲存储器来管理存储器的方法，系统和计算机程序。 一种方法包括当读取请求导致存储器高速缓存中的未命中时，确定与SSD读取请求相对应的数据是否可用的操作。 当SSD存储器中的数据可用时，从SSD存储器提供读取请求，并且当SSD存储器中的数据不可用时，调用SSD存储器跟踪逻辑，并从硬盘驱动器提供读取请求。 调用SSD存储器跟踪逻辑包括确定是否已经满足数据的获取准则，并且当满足获取标准时将与读取请求相对应的数据加载到SSD存储器中。 将SSD用作读取缓存可提高随机数据读取的内存性能。

公开(公告)号：US07523257B2

公开(公告)日：2009-04-21

申请号：US10793883

申请日：2004-03-08

申请人： Robert L. Horn ,  Virgil V. Wilkins

发明人： Robert L. Horn ,  Virgil V. Wilkins

IPC分类号： G06F12/00

CPC分类号： H04L67/1097 ,  G06F11/2087 ,  G06F2211/1035

摘要： A method of managing bad blocks in a RAID storage system. The system restores physical storage media and stripe redundancy by reassigning sectors and creating a bad block tracking structure. The bad block tracking structure consists of a volume map, a redundancy group table, and a bad block table that stores a bad block list. Redundancy is achieved through RAID 1 or RAID 10 mirroring rather than through the parity restoration required by conventional systems. The tracking structure returns media error status data to the originating host on volume read commands. The structure accepts volume write data from the originating host and then deletes the bad block tracking structure.

摘要翻译： 一种在RAID存储系统中管理坏块的方法。 系统通过重新分配扇区并创建坏块跟踪结构来恢复物理存储介质和条带冗余。 坏块跟踪结构由存储错误块列表的卷映射，冗余组表和坏块表组成。 通过RAID 1或RAID 10镜像而不是通过常规系统所需的奇偶恢复来实现冗余。 跟踪结构将卷读取命令的介质错误状态数据返回给始发主机。 该结构接受来自始发主机的卷写入数据，然后删除坏块跟踪结构。

公开(公告)号：US07356730B2

公开(公告)日：2008-04-08

申请号：US11018114

申请日：2004-12-21

申请人： Thomas R. Ulrich ,  James R. Schweitzer ,  Gregory D. Bolstad ,  Jay G. Randall ,  John R. Staub ,  George W. Priester

发明人： Thomas R. Ulrich ,  James R. Schweitzer ,  Gregory D. Bolstad ,  Jay G. Randall ,  John R. Staub ,  George W. Priester

IPC分类号： G06F11/10 ,  G06F11/16 ,  G06F12/16

CPC分类号： G06F11/1076 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0689 ,  G06F2211/1004

摘要： A system and method for dynamic redistribution of parity groups is described. The system and method for dynamic redistribution of parity groups operates on a computer storage system that includes a plurality of disk drives for storing parity groups. Each parity group includes storage blocks. The storage blocks include one or more data blocks and a parity block that is associated with the data blocks. Each of the storage blocks is stored on a separate disk drive such that no two storage blocks from a given parity set reside on the same disk drive. The computer system further includes a redistribution module to dynamically redistribute parity groups by combining some parity groups to improve storage efficiency.

摘要翻译： 描述了用于奇偶校验组的动态重新分配的系统和方法。 用于奇偶校验组的动态重新分配的系统和方法在包括用于存储奇偶校验组的多个磁盘驱动器的计算机存储系统上操作。 每个奇偶校验组包括存储块。 存储块包括与数据块相关联的一个或多个数据块和奇偶校验块。 每个存储块存储在单独的磁盘驱动器上，使得来自给定奇偶校验集的两个存储块不存在于同一磁盘驱动器上。 计算机系统还包括再分配模块，通过组合一些奇偶校验组来动态地重新分配奇偶校验组以提高存储效率。

公开(公告)号：US20070220243A1

公开(公告)日：2007-09-20

申请号：US11801650

申请日：2007-05-09

申请人： Fadi Mahmoud

发明人： Fadi Mahmoud

IPC分类号： G06F12/00

CPC分类号： G06F9/4401

摘要： A method for managing use of a fixed memory space of a computer system is provided. The computer system interfaces with controllers for managing operation of devices that operate with the computer system. The method includes determining whether sufficient memory is allocated in the fixed memory space for initializing code for the controllers, and jumping to swappable portion of the fixed memory space. The method also includes executing code in the swappable portion of the fixed memory space. The method further includes loading additional code needed to initialize the controllers from an external memory chip to the fixed memory space where the additional code is executed to complete initialization of the controllers of the computer system.