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公开(公告)号：US12001638B2
公开(公告)日：2024-06-04
申请号：US17790039
申请日：2021-05-12
Inventor： Yanwei Ren , Min Liu
IPC: G06F3/044 , G02F1/1362 , G02F1/1368 , G06F3/041
CPC classification number: G06F3/0446 , G02F1/136209 , G02F1/1368 , G06F3/04164 , G06F2203/04103
Abstract: A display substrate includes a first base, touch signal lines and touch units. The touch signal lines are disposed on a side of the first base, and lengths of at least two touch signal lines decrease in sequence. The touch units are disposed on a side of the touch signal lines away from the first base, and a touch unit is electrically connected to a touch signal line. Resistances of at least two touch units increase in sequence, and the at least two touch units in an increase order of the resistances in sequence are electrically connected to the at least two touch signal lines in a decrease order of the lengths in sequence, respectively. The touch units each include a touch electrode, and at least one of the at least two touch units further includes an auxiliary electrode stacked with and electrically connected to a touch electrode.
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公开(公告)号：US11901375B2
公开(公告)日：2024-02-13
申请号：US17765304
申请日：2021-04-13
Inventor： Yongbo Ju , Pengfei Cui , Jian Sun , Deshuai Wang , Xiangkai Shen , Jianbin Gao , Jiannan Wang , Guangshuai Wang
IPC: G02F1/1345 , H01L27/12 , G06F3/044 , G06F3/041 , G02F1/1333 , H01L23/00 , G02F1/1368
CPC classification number: H01L27/1244 , G02F1/13338 , G02F1/13458 , G06F3/0412 , G06F3/0445 , G06F3/04164 , H01L24/03 , H01L24/05 , H01L27/1259 , G02F1/13452 , G02F1/13685 , G06F2203/04103 , H01L24/06 , H01L2224/0345 , H01L2224/0362 , H01L2224/03614 , H01L2224/05008 , H01L2224/05013 , H01L2224/0518 , H01L2224/05073 , H01L2224/05124 , H01L2224/05138 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05553 , H01L2224/05566 , H01L2224/05573 , H01L2224/05686 , H01L2224/06165 , H01L2924/0106 , H01L2924/0132 , H01L2924/0549
Abstract: An array substrate has a display area and a bonding area located on a side of the display area. The array substrate includes a base, a plurality of first transistors, a plurality of conductive pins and a plurality of conductive electrodes. The plurality of first transistors are disposed on a side of the base and located in the display area; a first transistor includes a first gate, a first source and a first drain. The plurality of conductive pins are disposed on the side of the base and located in the bonding area, and are disposed in a same layer as the first gate. The plurality of conductive electrodes are each disposed on a respective one of surfaces of the plurality of conductive pins away from the base.
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公开(公告)号：US11874573B2
公开(公告)日：2024-01-16
申请号：US17777836
申请日：2021-01-15
Inventor： Peirong Huo , Shun Zhao , Peng Luo , Delong Zhong , Zhiqiang Wang
IPC: G02F1/1362 , G02F1/133 , G02F1/1333 , G06F3/041 , G02F1/1335 , G06F3/044 , G06F3/045 , G02F1/1343 , G02F1/1368
CPC classification number: G02F1/136218 , G02F1/13306 , G02F1/13338 , G02F1/133512 , G02F1/133514 , G06F3/044 , G06F3/045 , G06F3/0412 , G02F1/1368 , G02F1/13439 , G06F2203/04107
Abstract: A touch display device includes a backlight module (2) comprising a backlight iron frame (22); and a liquid crystal touch display panel (1) arranged on a light-emitting side of the backlight module; the liquid crystal touch display panel includes a touch electrode (11); and a compensation electrode (R) arranged on a side of the touch electrode facing the backlight module. The compensation electrode and the backlight iron frame are electrically connected with a ground signal terminal; and the touch electrode and the compensation electrode constitute a capacitor (C), a product of a capacitance value of the capacitor and a resistance value of the compensation electrode is smaller than a pulse width of a touch signal applied on the touch electrode, and an order of magnitude of the product is smaller than an order of magnitude of the pulse width of the touch signal.
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公开(公告)号：US11837125B2
公开(公告)日：2023-12-05
申请号：US17531247
申请日：2021-11-19
Inventor： Qianqian Zhang , Liangliang Liu , Liman Peng , Zhiyong Xue , Le Gao
IPC: G09G3/00
CPC classification number: G09G3/006 , G09G2300/0443 , G09G2310/08 , G09G2330/02 , G09G2370/20 , G09G2370/22
Abstract: A display panel, a method for detecting a display panel and an electronic device are provided. a display panel are provided, including a display area and a peripheral region surrounding the display area; a plurality of bonding pads in the peripheral region; a lighting pad in the peripheral region; a plurality of source signal lines at least in the display region; a plurality of source signal line leads in the peripheral region and electrically connected to the plurality of source signal lines and electrically connected to the plurality of bonding pads; a plurality of sub-pixel columns in the display region and electrically connected to the plurality of source signal lines; and a detection circuit, arranged in the peripheral region and between the plurality of binding pads and the display area.
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公开(公告)号：US20230343874A1
公开(公告)日：2023-10-26
申请号：US18343279
申请日：2023-06-28
Inventor： Yanqing CHEN , Jianyun XIE , Wei LI , Cheng LI , Pan GUO , Yanfeng LI , Weida QIN , Ning WANG
IPC: H01L29/786 , H01L23/552 , H01L27/12
CPC classification number: H01L29/78633 , H01L23/552 , H01L27/1259
Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
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Patent Agency Ranking
576.发明授权公开(公告)号：US11791278B2
公开(公告)日：2023-10-17
申请号：US17483822
申请日：2021-09-24
Inventor： Lei Yao , Feng Li , Lei Yan , Kai Li , Chenglong Wang , Teng Ye , Lin Hou , Xiaofang Li
IPC: H01L23/544 , H01L27/12
CPC classification number: H01L23/544 , H01L27/1248 , H01L27/1259 , H01L2223/54426
Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.
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577.发明授权公开(公告)号：US11735597B2
公开(公告)日：2023-08-22
申请号：US16631335
申请日：2018-12-21
Inventor： Wenlong Zhang , Xu Zhang , Wei Zhang , Jianfei Tian , Jingyi Xu , Shuai Han
IPC: H01L27/12 , G02F1/1362 , G02F1/1345
CPC classification number: H01L27/124 , G02F1/13458 , G02F1/13629 , H01L27/1237 , H01L27/1244 , H01L27/1259
Abstract: An array substrate, includes: a substrate, three metal layers stacked on the substrate, and a plurality of signal line leads disposed in a peripheral area of the array substrate. The plurality of signal line leads are distributed in at least two of the three metal layers.
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公开(公告)号：US11728435B2
公开(公告)日：2023-08-15
申请号：US17845568
申请日：2022-06-21
Inventor： Yanqing Chen , Jianyun Xie , Wei Li , Cheng Li , Pan Guo , Yanfeng Li , Weida Qin , Ning Wang
IPC: H01L29/786 , H01L27/12 , H01L23/552
CPC classification number: H01L29/78633 , H01L23/552 , H01L27/1259
Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.
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公开(公告)号：US20230194929A1
公开(公告)日：2023-06-22
申请号：US17926956
申请日：2021-09-01
Inventor： Long SUN , Wenlong ZHANG , Xin ZHAO , Yanwei REN , Yanhao SUN , Huijie ZHANG , Jingwei HOU
IPC: G02F1/1339 , G02F1/1335 , G02F1/1333
CPC classification number: G02F1/1339 , G02F1/133512 , G02F1/133357 , G02F2202/103
Abstract: A liquid crystal display panel (100) and a display apparatus (200). The liquid crystal display panel (100) includes a color filter substrate (1), an array substrate (2), and a sealant (3). An amorphous silicon layer (4) and a first interlayer dielectric (5) are provided between a shading layer (12) and a first substrate (11), a first through groove (12a) is formed in the shading layer (12) and the amorphous silicon layer (4), and a part of the sealant (3) is filled in the first through groove (12a) and is in direct contact with the first interlayer dielectric (5); and/or a planarization layer (22) is wrapped with a second interlayer dielectric (6), such that the planarization layer (22) is respectively separated from the sealant (3) and a second substrate (21), and the second interlayer dielectric (6) is in direct contact with the sealant (3). The phenomenon of film separation in a liquid crystal display panel is effectively alleviated, and the reliability of the liquid crystal display panel is improved.
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公开(公告)号：US20230163200A1
公开(公告)日：2023-05-25
申请号：US17771720
申请日：2021-03-08
Inventor： Xinguo WU , Fengguo WANG , Liang TIAN , Yu FENG , Bin LIU , Chenglong WANG , Yuxuan MA
IPC: H01L29/66 , H01L29/786
CPC classification number: H01L29/6675 , H01L29/78696 , H01L29/78672
Abstract: A method for manufacturing a display substrate is provided. The method includes: forming a first active layer arranged in the NMOS transistor region and a second active layer arranged in the PMOS transistor region on the base substrate; coating one side, facing away from the base substrate, of the first active layer and one side, facing away from the base substrate, of the second active layer with a first photoresist layer, forming a first pattern layer by patterning the first photoresist layer to expose at least two ends of the first active layer; forming N-type heavily doped regions by performing N-type heavy doping on the two ends of the first active layer with the first pattern layer as a mask; forming a second pattern layer by processing the first pattern layer to expose at least a middle region of the first active layer.
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