公开(公告)号：US20030223519A1

公开(公告)日：2003-12-04

申请号：US10404046

申请日：2003-04-02

申请人： Samsung Electronics Co., Ltd.

发明人： Jin-Hee Jeong ,  Jae-Hyon Kim

IPC分类号： H04B001/10 ,  H04N005/21

CPC分类号： H04N5/211 ,  H04N5/08 ,  H04N5/4401

摘要： An equalizer for a VSB receiver, which enables equalizations using segment synchronization information, has an extraction unit extracting the segment synchronization information included in the VSB broadcast signal, a storage unit storing the extracted segment synchronization information, and an equalization unit equalizing the VSB broadcast signal based on the segment synchronization information stored in the storage unit. The storage unit stores the segment synchronization information extracted from the extraction unit by field unit or by unit of N data segments within the field according to a channel state. More stable equalizations can be carried out in channel environment changes by storing segment synchronization information by the predetermined number of data segments and equalizing data within a corresponding data segment in a training mode while using the segment synchronization information every matching number of data segments.

摘要翻译： 用于使用段同步信息进行均衡的VSB接收机的均衡器具有提取单元，提取包括在VSB广播信号中的段同步信息，存储单元存储所提取的段同步信息，以及均衡单元使VSB广播信号均衡 基于存储在存储单元中的段同步信息。 存储单元根据信道状态，通过场单元或场内的N个数据段的单位存储从提取单元提取的段同步信息。 通过将段同步信息存储在预定数量的数据段，并且在训练模式中相应的数据段内的数据均衡，同时每个匹配的数据段使用段同步信息，可以在通道环境变化中执行更稳定的均衡。

公开(公告)号：US06621523B2

公开(公告)日：2003-09-16

申请号：US10078432

申请日：2002-02-21

申请人： Toshiro Obitsu

发明人： Toshiro Obitsu

IPC分类号： H04N1100

CPC分类号： H04N5/63 ,  G06F1/3203 ,  G06F1/3265 ,  G09G5/00 ,  G09G5/006 ,  G09G5/12 ,  G09G5/36 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/022 ,  H04N5/08 ,  H04N5/10 ,  Y02D10/153

摘要： A video signal processing circuit, in which a horizontal synchronizing signal is separated from an input analog video signal by a synchronism separating circuit, whether a “H” period of the horizontal synchronizing signal continues for more than a prespecified period of time or not is checked by a synchronizing signal monitoring counter, and power supply to an A/D converter is controlled thereby according to a result the confirmation.

公开(公告)号：US06614490B2

公开(公告)日：2003-09-02

申请号：US09758204

申请日：2001-01-12

申请人： Sung Ryong Hong ,  Young Mo Gu

发明人： Sung Ryong Hong ,  Young Mo Gu

IPC分类号： H04N544

CPC分类号： H04N5/455 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/046 ,  H04L7/06 ,  H04N5/08 ,  H04N5/4401 ,  H04N21/4382

摘要： A digital television (TV) receiver using a vestigial sideband (VSB) system, and timing recovering apparatus and method for the digital TV receiver are disclosed. The timing error can be compensated for by rapidly and accurately searching the position of the segment sync signal using the Hilbert filter even if the strong 2-symbol-delayed ghost is applied. Also, the tracking performance for the timing error and the zitter performance can be improved by extracting the timing error information even from the signal having passed through the Hilbert filter.

摘要翻译： 公开了一种使用残留边带（VSB）系统的数字电视（TV）接收机，以及数字电视接收机的定时恢复装置和方法。 即使施加强2符号延迟的重影，也可以使用希尔伯特滤波器快速准确地搜索段同步信号的位置来补偿定时误差。 此外，即使通过希尔伯特滤波器的信号，也可以通过提取定时误差信息来提高定时误差和抖动性能的跟踪性能。

公开(公告)号：US06614487B2

公开(公告)日：2003-09-02

申请号：US09758422

申请日：2001-01-12

申请人： Sung Ryong Hong ,  Young Mo Gu

发明人： Sung Ryong Hong ,  Young Mo Gu

IPC分类号： H04N506

CPC分类号： H04N7/56 ,  H04N5/08 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/4382

摘要： An apparatus and method for detecting a synchronizing signal in a digital TV receiver which adopts a VSB mode is disclosed. The apparatus includes a correlation unit for obtaining a correlation value between a received signal for each unit of symbols and a preset reference field synchronizing signal, a maximum value detector for detecting a location of the symbol having a maximum correlation value while performing counting operation for a unit of a variable constant added to the number of symbols corresponding to one field, a synchronizing lock signal generator for generating a synchronizing lock signal by testing reliability of the symbol location detected by the maximum value detector, and a synchronizing location controller for calculating a relative location of the symbol location having a maximum value to generate a corresponding synchronizing signal if the synchronizing lock signal is generated by the synchronizing lock signal generator. A synchronizing pattern is traced per field in even case that channel characteristic is seriously varied. Thus, the synchronizing signals are stably restored at high speed.

摘要翻译： 公开了一种在采用VSB模式的数字TV接收机中检测同步信号的装置和方法。 该装置包括：相关单元，用于获得每个符号单元的接收信号与预设的参考场同步信号之间的相关值;最大值检测器，用于检测具有最大相关值的符号的位置，同时执行针对 增加到与一个场相对应的符号数的可变常数的单位;同步锁定信号发生器，用于通过测试由最大值检测器检测到的符号位置的可靠性产生同步锁定信号;以及同步位置控制器，用于计算相对 如果同步锁定信号由同步锁定信号发生器产生，则具有最大值的符号位置的位置以产生对应的同步信号。 即使在信道特性严重变化的情况下，每个字段也跟踪同步模式。 因此，同步信号被高速稳定地恢复。

公开(公告)号：US06600778B1

公开(公告)日：2003-07-29

申请号：US09131397

申请日：1998-08-07

申请人： Ho Jun Nam

发明人： Ho Jun Nam

IPC分类号： H03H730

CPC分类号： H04N5/4401 ,  H04L7/044 ,  H04L2025/03382 ,  H04N5/08 ,  H04N5/211

摘要： The HDTV receiver system includes a pre-detection processor to filter a digitized signal before detecting the sync signal. The pre-detection processor eliminates the effects of ghost signal which can cause distortion of the original sync signal. The pre-detection processor can be a tapped-delay-line filter, a blind mode equalizer, or both.

摘要翻译： HDTV接收机系统包括在检测同步信号之前对数字化信号进行滤波的预检测处理器。 预检测处理器消除了可能导致原始同步信号失真的重影信号的影响。 预检测处理器可以是抽头延迟线滤波器，盲模均衡器或两者。

公开(公告)号：US06519304B1

公开(公告)日：2003-02-11

申请号：US09232136

申请日：1999-01-15

申请人： Allen LeRoy Limberg

发明人： Allen LeRoy Limberg

IPC分类号： H04N508

CPC分类号： H04N5/4401 ,  H04N5/08

摘要： A digital television signal receiver includes a bin amplitude comparator for symbol decoding and match filtering to recover data synchronizing information from selected bin amplitude comparator responses generated during data slicing. The bin amplitude comparator concurrently supplies bin occupancy results for an amplitude slice including a value +S and for an amplitude slice including a value −S, which values +S and −S define the positive and negative excursions respectively of a binary data synchronization signal, current bin occupancy results being grouped together as two-parallel-bit serial input signal to a shift register clocked at symbol rate. Match filtering to detect data segment synchronization symbol code sequences is provided in accordance with an aspect of the invention by an AND gate supplied bits from selected storage locations in the shift register as wired input signals. In other match filtering performed in accordance with another aspect of the invention, a digital adder network receives bits from selected storage locations in the shift register as wired input signals, and a threshold detector responds to the summed bits exceeding a threshold value to detect data field synchronization symbol code sequences.

公开(公告)号：US20020075406A1

公开(公告)日：2002-06-20

申请号：US10078432

申请日：2002-02-21

申请人： Fujitsu Limited

发明人： Toshiro Obitsu

IPC分类号： H04N011/00 ,  H04N005/63

CPC分类号： H04N5/63 ,  G06F1/3203 ,  G06F1/3265 ,  G09G5/00 ,  G09G5/006 ,  G09G5/12 ,  G09G5/36 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/022 ,  H04N5/08 ,  H04N5/10 ,  Y02D10/153

摘要： A video signal processing circuit, in which a horizontal synchronizing signal is separated from an input analog video signal by a synchronism separating circuit, whether a nullHnull period of the horizontal synchronizing signal continues for more than a prespecified period of time or not is checked by a synchronizing signal monitoring counter, and power supply to an A/D converter is controlled thereby according to a result the confirmation.

公开(公告)号：US20020060676A1

公开(公告)日：2002-05-23

申请号：US09900162

申请日：2001-07-09

发明人： Young-Chan Kim

IPC分类号： G09G005/00

CPC分类号： G09G5/006 ,  H04N5/08 ,  H04N5/4401 ,  H04N5/44513 ,  H04N5/46 ,  H04N21/4122 ,  H04N21/485

摘要： An apparatus and a method for determining a type of DVI (Digital Visual Interface) connector connected to a digital video display device, wherein the apparatus utilizes a first resistor connected between a voltage source and a node; a second resistor connected between the node and a ground terminal; a DVI receptacle connected to the DVI connector, the DVI receptacle having a plurality of digital signal sockets connected to receive digital signals output from a host and a plurality of analog signal sockets connected to receive analog signals output from the host, the node being connected to a predetermined one of the analog signal sockets; and a controller connected to the node, the controller determining the DVI connector to be a DVI-D (digital only) type connector when a low voltage is detected at the node, and determining the DVI connector to be a DVI-I (digital and analog) type connector when a high voltage is detected at the node.

摘要翻译： 一种用于确定连接到数字视频显示设备的DVI（数字视频接口）连接器类型的装置和方法，其中所述设备利用连接在电压源和节点之间的第一电阻器; 连接在节点和接地端子之间的第二电阻器; 连接到DVI连接器的DVI插座，DVI插座具有连接以接收从主机输出的数字信号的多个数字信号插座和连接以接收从主机输出的模拟信号的多个模拟信号插座，所述节点连接到 模拟信号插座中的预定的一个; 以及连接到节点的控制器，当在节点处检测到低电压时，控制器将DVI连接器确定为DVI-D（仅数字）型连接器，并且将DVI连接器确定为DVI-I（数字和 模拟）型连接器，当在节点处检测到高电压时。

公开(公告)号：US06380982B1

公开(公告)日：2002-04-30

申请号：US09040424

申请日：1998-03-18

申请人： Toshiro Obitsu

发明人： Toshiro Obitsu

IPC分类号： H04N700

CPC分类号： H04N5/63 ,  G06F1/3203 ,  G06F1/3265 ,  G09G5/00 ,  G09G5/006 ,  G09G5/12 ,  G09G5/36 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/022 ,  H04N5/08 ,  H04N5/10 ,  Y02D10/153

摘要： A video signal processing circuit, in which a horizontal synchronizing signal is separated from an input analog video signal by a synchronism separating circuit, whether a “H” period of the horizontal synchronizing signal continues for more than a prespecified period of time or not is checked by a synchronizing signal monitoring counter, and power supply to an A/D converter is controlled thereby according to a result the confirmation.

摘要翻译： 一个视频信号处理电路，其中水平同步信号通过同步分离电路与输入的模拟视频信号分离，水平同步信号的“H”周期是否持续超过预定的时间段被检查 通过同步信号监视计数器，并且根据结果来控制对A / D转换器的电源的确认。

公开(公告)号：US20010041042A1

公开(公告)日：2001-11-15

申请号：US09086338

申请日：1998-05-29

发明人： SEUNG-TAEK LEE

IPC分类号： H04N005/92

CPC分类号： G09G5/18 ,  G09G1/04 ,  G09G2340/125 ,  H04N5/08 ,  H04N5/46 ,  H04N9/641

摘要： A sync signal reproducing circuit for a composite video signal, includes a channel selector for receiving a first composite video signal and a second composite video signal output from a composite video signal input stage, and also receiving a composite video signal selection signal output from a microcomputer, to thereby selectively output the first and second composite video signals; a D-COM filter for receiving the composite video signal selected by the channel selector, and separately outputting its chrominance signal and luminance signal; and a chroma circuit for receiving the chrominance signal and luminance signal of the composite video signal output from the D-COM filter, and thus reproducing the chrominance signal and separating horizontal and vertical sync signals from the luminance signal. The reproducing circuit stably separates the horizontal and vertical sync signals from the luminance of a composite video signal, and the separated sync signals enable the composite video signal and the VGA video signal to be discriminated.

摘要翻译： 一种用于复合视频信号的同步信号再现电路，包括：用于接收从复合视频信号输入级输出的第一复合视频信号和第二复合视频信号的频道选择器，并且还接收从微计算机输出的复合视频信号选择信号 从而选择性地输出第一和第二复合视频信号; D-COM滤波器，用于接收由频道选择器选择的复合视频信号，并分别输出其色度信号和亮度信号; 以及色度电路，用于接收从D-COM滤波器输出的复合视频信号的色度信号和亮度信号，从而再现色度信号，并从亮度信号中分离水平和垂直同步信号。 再现电路根据复合视频信号的亮度稳定地分离水平和垂直同步信号，并且分离的同步信号使得能够区分复合视频信号和VGA视频信号。