公开(公告)号：US20060028874A1

公开(公告)日：2006-02-09

申请号：US11241000

申请日：2005-09-29

Applicant: Raul-Adrian Cernea

Inventor： Raul-Adrian Cernea

IPC: G11C11/34

CPC classification number: G11C16/06 ,  G11C7/1036 ,  G11C7/1051 ,  G11C19/00 ,  G11C19/28

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

公开(公告)号：US20050276104A1

公开(公告)日：2005-12-15

申请号：US11207919

申请日：2005-08-19

Applicant: Todd Merritt ,  Donald Morgan

Inventor： Todd Merritt ,  Donald Morgan

IPC: G11C7/10 ,  G11C11/34 ,  G11C11/4096

CPC classification number: G11C7/106 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  G11C2207/107

Abstract: A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

Abstract translation: 一种用于减少存储器件中所需的数据读取线数量的存储器件。 具体来说，使用多个辅助触发器来预取存储器件中的数据。 辅助触发器被配置为以交替周期性方式从4位预取中锁存一个或两个数据位，从而需要更少的数据线。

公开(公告)号：US06895465B2

公开(公告)日：2005-05-17

申请号：US10816076

申请日：2004-03-31

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00 ,  G06F12/02

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US20040190347A1

公开(公告)日：2004-09-30

申请号：US10818887

申请日：2004-04-05

Inventor： Raul-Adrian Cernea

IPC: G11C005/00

CPC classification number: G11C16/06 ,  G11C7/1036 ,  G11C7/1051 ,  G11C19/00 ,  G11C19/28

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 存储单元可以是多状态存储器单元。 有一个移位寄存器链，具有数组列的阶段。 选通脉冲通过该移位寄存器移位。 每个时钟的选通点依次处于并使能不同的选择电路。 那个已经被选通使能的特定选择电路然后将执行一定的功能。 在读取模式下，所选择的选择电路将存储的信息发送到输出缓冲器，以从集成电路输出。 而在编程模式下，所选择的选择电路将从输入缓冲器接收数据。 该数据将被写入存储单元。

公开(公告)号：US06748483B2

公开(公告)日：2004-06-08

申请号：US10452744

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06735668B2

公开(公告)日：2004-05-11

申请号：US10452619

申请日：2003-06-02

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US20040085818A1

公开(公告)日：2004-05-06

申请号：US10284198

申请日：2002-10-31

Inventor： William Thomas Lynch ,  David James Herbison

IPC: G11C005/00

CPC classification number: G11C29/32 ,  G06F13/1673 ,  G11C7/1036 ,  G11C29/12 ,  G11C29/1201 ,  G11C2029/3202

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract translation: 一种存储器访问方案，其采用串联互连的一组或多组移位寄存器，数据可以从其中加载或写入一个或多个存储器件。 也就是说，来自存储器件的数据可以并行加载到移位寄存器组中，然后通过移位寄存器串行移位，直到从移位寄存器组输出并传送到其目的地。 此外，数据可以从/从该组移位寄存器中读取并加载到存储器件中，使得在读取和/或加载数据期间移位寄存器的移位是不间断的。 此外，来自存储器件的数据可以被加载到两个或更多个并行的移位寄存器链中，然后通过移位寄存器链串行移位。

公开(公告)号：US06728828B2

公开(公告)日：2004-04-27

申请号：US10445134

申请日：2003-05-23

Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

IPC: G11C804

CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).

Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

公开(公告)号：US06704828B1

公开(公告)日：2004-03-09

申请号：US09652390

申请日：2000-08-31

Applicant: Todd A. Merritt ,  Donald M. Morgan

Inventor： Todd A. Merritt ,  Donald M. Morgan

IPC: G06F1338

CPC classification number: G11C7/106 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4096 ,  G11C2207/107

Abstract: A method and apparatus for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.

Abstract translation: 一种用于减少存储器件中所需的数据读取线数量的方法和装置。 具体来说，使用多个辅助触发器来预取存储器件中的数据。 辅助触发器被配置为以交替周期性方式从4位预取中锁存一个或两个数据位，从而需要更少的数据线。

公开(公告)号：US06667923B1

公开(公告)日：2003-12-23

申请号：US10205862

申请日：2002-07-26

Applicant: Gregory Jay DelMain ,  John Gord ,  Lawrence J. Karr ,  Paul De Rocco ,  Glenn A. DeMichele ,  Douglas Kerns ,  Andrew Barber

Inventor： Gregory Jay DelMain ,  John Gord ,  Lawrence J. Karr ,  Paul De Rocco ,  Glenn A. DeMichele ,  Douglas Kerns ,  Andrew Barber

IPC: G11C702

CPC classification number: G11C7/1036

Abstract: An apparatus and method for forming a RAM data memory that generates predictable noise/interference components that are coherent with each write cycle and essentially independent of the data content of the RAM data memory. The RAM data memory is comprised of a plurality of cells, each representing a data bit, which are selectively addressable as memory bytes formed of multiple bits. Each cell is formed of two sets of cross-coupled transistors. By causing each set of cross-coupled transistors to be set to a common voltage level at the beginning of a write cycle before setting one set of transistors to a low level and the one set of transistors to be set to a high level (thus representing a desired data bit value), the associated noise/interference components of the power drain are data independent. Furthermore, the data-independent noise occurs at frequencies at or above the write cycle rate.

Abstract translation: 一种用于形成RAM数据存储器的装置和方法，所述RAM数据存储器产生与每个写周期相干并且基本上独立于RAM数据存储器的数据内容的可预测的噪声/干扰分量。 RAM数据存储器由多个单元组成，每个单元表示数据位，其可选择地可寻址为由多位形成的存储器字节。 每个单元由两组交叉耦合晶体管组成。 通过在将一组晶体管设置为低电平并且将一组晶体管设置为高电平（从而代表一个晶体管的一组）之前，将每组交叉耦合晶体管设置为写周期开始时的公共电压电平 期望的数据位值），功率相关的噪声/干扰分量是数据无关的。 而且，数据无关的噪声出现在等于或高于写周期速率的频率。