公开(公告)号：US07302624B2

公开(公告)日：2007-11-27

申请号：US11213327

申请日：2005-08-25

Applicant: Janusz Rajski ,  Grzegorz Mrugalski ,  Artur Pogiel ,  Jerzy Tyszer ,  Chen Wang

Inventor： Janusz Rajski ,  Grzegorz Mrugalski ,  Artur Pogiel ,  Jerzy Tyszer ,  Chen Wang

IPC: G01R31/28

CPC classification number: G01R31/318547 ,  G01R31/31703 ,  G01R31/318536 ,  G01R31/318566 ,  G01R31/318583 ,  G01R31/31921 ,  G11C29/40 ,  G11C29/48 ,  G11C2029/3202

Abstract: Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

Abstract translation: 本文公开了用于诊断来自压缩测试响应的故障扫描单元的方法，装置和系统。 例如，在一个非限制性示例性实施例中，接收指示在一个或多个对应的压缩测试响应中存在一个或多个错误的一个或多个签名。 通过分析签名来识别导致错误的电路不足测试中的扫描单元。 在该示例性实施例中，分析包括选择至少部分地基于与扫描小区候选者相关联的权重值来潜在地引起压缩测试响应中的错误的扫描小区候选，该权重值表示扫描单元 候选人造成错误。 还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的有形计算机可读介质。 还提供了包括由任何所公开的方法识别的故障扫描单元的列表的有形计算机可读介质。

公开(公告)号：US07283404B2

公开(公告)日：2007-10-16

申请号：US11055830

申请日：2005-02-11

Applicant: Masood Ahmed Khan ,  Michael Ju Hyeok Lee ,  Ed Seewann

Inventor： Masood Ahmed Khan ,  Michael Ju Hyeok Lee ,  Ed Seewann

IPC: G11C16/04

CPC classification number: G11C29/022 ,  G11C15/00 ,  G11C29/02 ,  G11C2029/3202

Abstract: A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functional mode, input data bypasses the master latch and transports directly to the CBL output via the slave latch. The CBL effectively removes the master latch from the circuit in the high speed functional mode. However, in the lower speed test mode, input test data travels via both the master and slave latches to the CBL output.

Abstract translation: 公开了一种内容可寻址存储器（CAM）系统，其包括双模周期边界锁存器（CBL）。 CBL包括耦合到从锁存器的主锁存器。 CBL以高速功能模式和较低速度测试模式运行。 在高速功能模式下，输入数据绕过主机锁存器，并通过从机锁存器直接传输到CBL输出。 CBL在高速功能模式下有效地从电路中去除主锁存器。 然而，在较低速度测试模式下，输入测试数据通过主锁存器和从器件锁存器传输到CBL输出。

公开(公告)号：US20070230255A1

公开(公告)日：2007-10-04

申请号：US11487514

申请日：2006-07-17

Applicant: Ryo Fukuda

Inventor： Ryo Fukuda

IPC: G11C7/00

CPC classification number: G11C7/20 ,  G11C29/802 ,  G11C2029/3202

Abstract: A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.

Abstract translation: 使用初始化数据操作的半导体存储器件包括锁存初始化数据的第一锁存电路，包括多个存储器单元并具有第一区域和第二区域的存储单元阵列，第一区域存储数据，以及缓冲电路 具有访问第一锁存电路的功能，缓冲电路向第二区域传送从第一锁存电路传送的初始化数据，并将从第二区域传送的初始化数据传送到第一锁存电路。

公开(公告)号：US20070168776A1

公开(公告)日：2007-07-19

申请号：US11243898

申请日：2005-10-04

Applicant: William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

Inventor： William Grose ,  Lonnie Lambert ,  Jeanne Krayer Pitz ,  Toru Tanaka

IPC: G11C29/00

CPC classification number: G11C29/12 ,  G11C16/04 ,  G11C29/48 ,  G11C2029/3202

Abstract: Systems, methods and circuits for implementing efficient device testing. As one example, a method is disclosed for testing a device that includes both a digital and analog portion. In some cases, the digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. Each of the plurality of selector devices is electrically coupled to a respective one of the memory cells, is at least indirectly coupled to one of the plurality of latch, devices, and is controlled by a selector input. In the method, a load clock is applied to the plurality of latch devices such that a pattern is loaded into the plurality of latch devices. The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices. A system clock is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.

Abstract translation: 用于实现高效设备测试的系统，方法和电路。 作为一个示例，公开了一种用于测试包括数字和模拟部分的设备的方法。 在一些情况下，数字部分包括多个锁存装置，并且模拟部分包括多个存储器单元和多个选择器装置。 多个选择器装置中的每一个电耦合到相应的一个存储单元，至少间接耦合到多个锁存器件中的一个，并由选择器输入端控制。 在该方法中，将负载时钟施加到多个锁存装置，使得模式被加载到多个锁存装置中。 选择器输入被断言，使得图案的导数被多个选择器接收并返回到多个锁存装置。 系统时钟被施加到多个锁存装置，使得图案的导数被加载到多个锁存装置中。

公开(公告)号：US20070143647A1

公开(公告)日：2007-06-21

申请号：US11304854

申请日：2005-12-15

Applicant: Edgardo Klass

Inventor： Edgardo Klass

IPC: G11C29/00

CPC classification number: G01R31/318533 ,  G01R31/318544 ,  G11C2029/3202

Abstract: In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an input connected to a scan data input to the storage circuit and further coupled to receive a scan enable input. The scan latch is configured to store the scan data input responsive to an assertion of the scan enable input, and also comprises a second passgate connected to the storage node and having an input coupled to receive the stored scan data. Each of the first passgate and the second passgate are coupled to receive respective pairs of control signals to control opening and closing of the passgates, wherein the scan enable signal controls which of the respective pairs of control signals are pulsed. In this manner, only one of the first passgate and the second pass-gate is opened in a given clock cycle of a clock signal from which the pulses are generated.

Abstract translation: 在一个实施例中，存储电路包括第一通道门，其具有耦合以输入表示向存储电路输入的数据的信号的输入，并且还具有连接到存储电路中的存储节点的输出。 存储电路还包括扫描锁存器，其具有连接到输入到存储电路的扫描数据的输入，并进一步耦合以接收扫描使能输入。 扫描锁存器被配置为响应于扫描使能输入的断言来存储扫描数据输入，并且还包括连接到存储节点并具有耦合以接收所存储的扫描数据的输入的第二通道。 第一通道和第二通道中的每一个被耦合以接收相应的控制信号对以控制通风门的打开和关闭，其中扫描使能信号控制相应的控制信号对中的哪一个是脉冲的。 以这种方式，在产生脉冲的时钟信号的给定时钟周期中仅打开第一通道和第二通道中的一个。

公开(公告)号：US20070136564A1

公开(公告)日：2007-06-14

申请号：US11302742

申请日：2005-12-14

Applicant: Sankaran Menon ,  John Fernando ,  Ravi Kolagotla

Inventor： Sankaran Menon ,  John Fernando ,  Ravi Kolagotla

IPC: G06F9/44

CPC classification number: G11C29/32 ,  G11C2029/3202

Abstract: Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.

Abstract translation: 一种装置，包括将保存/恢复链的第一保存/恢复单元的第一锁存器的输出连接到第一存储/恢复单元的第二锁存器的输入的保存路径，连接来自第一存储/恢复单元的输出的恢复路径 第二锁存器到第一锁存器的输入端，以及扫描路径，用于将第二锁存器的输出连接到保存/恢复链路的第二保存/恢复单元的输入。 该装置对于快速上下文切换是有用的。

公开(公告)号：US07222272B2

公开(公告)日：2007-05-22

申请号：US10430319

申请日：2003-05-07

Applicant: Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

Inventor： Yoshio Takazawa ,  Toshio Yamada ,  Kazumasa Yanagisawa ,  Takashi Hayasaka

IPC: G11C29/26 ,  G11C29/40

CPC classification number: G11C29/26 ,  G11C2029/1806 ,  G11C2029/2602 ,  G11C2029/3202

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract translation: 提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息 从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。 测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。 因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。 因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。

公开(公告)号：US07173840B2

公开(公告)日：2007-02-06

申请号：US10529331

申请日：2003-09-03

Applicant: Karlheinz Krause ,  Elke Tiemeyer

Inventor： Karlheinz Krause ,  Elke Tiemeyer

IPC: G11C5/06

CPC classification number: G11C29/30 ,  G11C2029/3202

Abstract: In order to program a memory module, some of its inputs are stimulated via internal memory locations of a so-called boundary scan (BSCAN) register that is provided in the form of an IC or ASIC. In order to activate or deactivate a write operation, the control signal input of the memory module, said control signal input being responsible for generating a WRITE_ENABLE signal, is controlled exclusively. The switching over of the WRITE_ENABLE signal from “LOW” to “HIGH” potential and vice versa thus ensues according to two JTAG instructions of an instruction sequence that provides for the generation of a LOW or HIGH level at the setting signal input or resetting signal input of an update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal. By appropriately modifying the control unit and the BSCAN cell, which stimulates the WRITE_ENABLE signal at the WR input of the memory module, the programming can be accelerated without having to expand the interface between the control unit and the BSCAN register to the board and equipment level. In another embodiment of the invention, a control unit automatically switches over the WRITE_ENABLE signal from “LOW” to “HIGH” potential or from HIGH to LOW potential at an appropriate or rather programmable point in time by setting or resetting the update flip-flop of the memory location responsible for generating the WRITE_ENABLE signal.

Abstract translation: 为了对存储器模块进行编程，其一些输入通过以IC或ASIC形式提供的所谓边界扫描（BSCAN）寄存器的内部存储单元进行激励。 为了激活或禁用写入操作，仅控制存储器模块的控制信号输入，所述控制信号输入负责产生WRITE_ENABLE信号。 WRITE_ENABLE信号从“低”电平切换到“高”电位，反之亦然，因此根据指令序列的两个JTAG指令，提供在设置信号输入或复位信号输入端产生低电平或高电平 存储器位置的更新触发器负责产生WRITE_ENABLE信号。 通过适当地修改在存储器模块的WR输入处刺激WRITE_ENABLE信号的控制单元和BSCAN单元，可以加速编程，而不必将控制单元和BSCAN寄存器之间的接口扩展到板和设备级 。 在本发明的另一个实施例中，控制单元通过设置或重置更新触发器来自动将WRITE_ENABLE信号从“低”电平切换到“高”电位或从适当或相当可编程的时间点从高电平切换到低电位 存储位置负责生成WRITE_ENABLE信号。

公开(公告)号：US07171600B2

公开(公告)日：2007-01-30

申请号：US10828263

申请日：2004-04-21

Applicant: Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

Inventor： Sadami Takeoka ,  Mitsuyasu Ohta ,  Osamu Ichikawa ,  Masayoshi Yoshimura

IPC: G01R31/28

CPC classification number: G01R31/28 ,  G01R31/318505 ,  G01R31/318538 ,  G01R31/318558 ,  G06F17/50 ,  G11C5/02 ,  G11C5/025 ,  G11C29/48 ,  G11C2029/3202 ,  H01L23/12

Abstract: An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract translation: 一种用于通过在公共半导体布线基板上安装多个芯片智能特性（IP）来测试半导体器件的装置，包括安装有芯片IP的硅布线基板。 通过将触发器连接到布线来测试布线中的连接，在硅布线基板上形成用于边界扫描测试的电路。 可以安排IP超级（IPOS）设备上的IP或每个芯片IP，以便在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

公开(公告)号：US20070011521A1

公开(公告)日：2007-01-11

申请号：US11423393

申请日：2006-06-09

Applicant: Prashant DUBEY

Inventor： Prashant DUBEY

IPC: G01R31/28

CPC classification number: G01R31/318533 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/48 ,  G11C29/50012 ,  G11C2029/0401 ,  G11C2029/3202

Abstract: An integrated scannable interface for testing memory. The interface includes a selection device for selecting a signal from at least two input signals responsive to an activation signal, a first storage device coupled to the output of the selection device for storing the signal responsive to a first enable signal and generating an output signal for the memory. The first storage device is connected at the input node of the memory, and a second storage device is coupled at its input to the first storage device for storing the output signal responsive to a second enable signal and generating a test signal for testing the memory. The output signal is observed for debugging faults between the integrated scannable interface and the memory and for debugging faults between the first and second storage devices.

Abstract translation: 用于测试内存的集成可扫描接口。 该接口包括用于响应于激活信号从至少两个输入信号中选择信号的选择装置，耦合到选择装置的输出的第一存储装置，用于响应于第一使能信号存储信号并产生输出信号 记忆。 第一存储装置连接在存储器的输入节点处，第二存储装置在其输入处耦合到第一存储装置，用于响应于第二使能信号存储输出信号，并产生用于测试存储器的测试信号。 观察输出信号用于集成可扫描接口和存储器之间的调试故障，并用于调试第一和第二存储设备之间的故障。