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    Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory
    41.
    发明授权
    Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory 有权
    半导体测试设备，半导体测试方法，半导体制造方法和半导体存储器

    公开(公告)号：US07137055B2

    公开(公告)日：2006-11-14

    申请号：US11012355

    申请日：2004-12-16

    申请人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

    发明人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

    IPC分类号： G06F11/00

    CPC分类号： G11C29/56004 ,  G01R31/31935 ,  G11C29/56

    摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

    摘要翻译： 根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式​​应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高 包装后的存储器和通过执行有缺陷的冗余处理。

    DOUBLE DATA RATE SCHEME FOR DATA OUTPUT
    43.
    发明申请
    DOUBLE DATA RATE SCHEME FOR DATA OUTPUT 有权
    用于数据输出的双重数据速率方案

    公开(公告)号：US20060198234A1

    公开(公告)日：2006-09-07

    申请号：US11380617

    申请日：2006-04-27

    申请人： Mark Thomann ,  Wen Li

    发明人： Mark Thomann ,  Wen Li

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1051 ,  G11C7/1039 ,  G11C7/1066

    摘要： Systems, devices, and methods for a double data rate memory device includes a storage element, a first pipeline, and a second pipeline. The pipelines are connected to the storage unit to pass or output data on rising and falling edges of an external clock signal. The device permits data transferring at dual data rates. Another memory device includes a storage element and a plurality of pipelines for transferring data. The plurality of pipelines each pass data on different events.

    摘要翻译： 用于双数据速率存储器设备的系统，设备和方法包括存储元件，第一管线和第二管线。 管线连接到存储单元以在外部时钟信号的上升沿和下降沿传递或输出数据。 该设备允许以双数据速率传输数据。 另一存储器件包括用于传送数据的存储元件和多个管线。 多个管道各自传递关于不同事件的数据。

    System and method for providing a double adder for decimal floating point operations
    44.
    发明申请
    System and method for providing a double adder for decimal floating point operations 失效

    公开(公告)号：US20060179103A1

    公开(公告)日：2006-08-10

    申请号：US11054687

    申请日：2005-02-09

    申请人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

    发明人： Steven Carlough ,  Wilhelm Haller ,  Wen Li ,  Eric Schwarz

    IPC分类号： G06F7/50

    CPC分类号： G06F7/4912 ,  G06F7/483 ,  G06F7/507

    摘要： A system for performing decimal floating point addition. The system includes input registers for inputting a first and second operand for an addition operation. The system also includes a plurality of adder blocks, each calculating a sum of one or more corresponding digits from the first operand and the second operand. Output from each of the adder blocks includes the sum of the corresponding digits and a carry out indicator for the corresponding digits. The calculating is performed during a first clock cycle. The system also includes an intermediate result register for storing the sums of the corresponding digits output from each of the plurality of adder blocks, the storing during the first clock cycle. The system further includes a carry chain for storing the carry out indicator output from each of the plurality of adder blocks, the storing occurring during the first clock cycle. The system further includes an incrementer for adding one to each of the sums stored in the intermediate result register, the incrementing occurring during a second clock cycle. In addition, a mechanism is provided for selecting between each of the sums and the sums incremented by one. The input to the mechanism includes the carry chain. The output includes the final sum of the first operand and the second operand. The selecting occurs during the second clock cycle.

    System and method for reduction of leading zero detect for decimal floating point numbers
    45.
    发明申请
    System and method for reduction of leading zero detect for decimal floating point numbers 审中-公开
    用于减小十进制浮点数的前导零检测的系统和方法

    公开(公告)号：US20060179098A1

    公开(公告)日：2006-08-10

    申请号：US11054234

    申请日：2005-02-09

    申请人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

    发明人： Michael Kelly ,  Wen Li ,  Eric Schwarz ,  Wai Wong

    IPC分类号： G06F7/38

    CPC分类号： G06F7/74 ,  G06F7/491 ,  G06F2207/4911

    摘要： A method for leading zero detection. The method includes receiving DPD encoded data representing a three digit BCD number and determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least one leading zero digit. A group one switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least one leading zero digit and set to one otherwise. The method also includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains at least two leading zero digits. A group two switch is set to zero if it was determined that the BCD number represented by the DPD encoded data contains at least two leading zero digits and set to one otherwise. The method further includes determining directly from the DPD encoded data if the BCD number represented by the DPD encoded data contains three leading zero digits. A group three switch is set to zero if was determined that the BCD number represented by the DPD encoded data contains three leading zero digits and set to one otherwise.

    摘要翻译： 一种引导零检测的方法。 如果由DPD编码数据表示的BCD数字包含至少一个前导零数字，则该方法包括接收表示三位BCD号码的DPD编码数据，并直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少一个前导零数字并且另外设置为一个，则将一组开关设置为零。 如果由DPD编码数据表示的BCD数字包含至少两个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含至少两个前导零数字并且另外设置为一个，则组二开关被设置为零。 如果由DPD编码数据表示的BCD数字包含三个前导零数字，则该方法还包括直接从DPD编码数据确定。 如果确定由DPD编码数据表示的BCD数字包含三个前导零数字并且另外设置为一个，则组三开关被设置为零。

    Corrosion protection using carbon coated electron collector for lithium-ion battery with molten salt electrolyte
    46.
    发明申请
    Corrosion protection using carbon coated electron collector for lithium-ion battery with molten salt electrolyte 失效
    使用具有熔融盐电解质的锂离子电池碳涂层电子收集器进行腐蚀保护

    公开(公告)号：US20060063072A1

    公开(公告)日：2006-03-23

    申请号：US11080592

    申请日：2005-03-15

    申请人： Wen Li ,  Junzo Ukai ,  Hiroaki Awano ,  Yutaka Oyama ,  Masaki Matsui ,  Gerald Perron ,  Michael Armand

    发明人： Wen Li ,  Junzo Ukai ,  Hiroaki Awano ,  Yutaka Oyama ,  Masaki Matsui ,  Gerald Perron ,  Michael Armand

    IPC分类号： H01M4/66

    CPC分类号： H01M4/661 ,  B82Y30/00 ,  H01M2/1653 ,  H01M4/663 ,  H01M4/667 ,  H01M10/0561 ,  H01M10/0563 ,  H01M2300/0022

    摘要： A battery, such as a lithium-ion battery, comprises a first electrode, a second electrode, a molten salt electrolyte, and an electron collector, associated with the first electrode, the electron collector comprising an electrically conducting film. The battery further includes a protection layer separating the electron collector and the first electrode, the protection layer comprising a carbon-containing material. The electron collector may be an electrically conducting material such as aluminum, aluminum alloy, copper, nickel, other metal (such as alloys), conducting polymer, and the like. In one example, the protection layer is a graphite layer. In other examples, the protection layer may be a fullerene film, carbon nanotube film, or other carbon-containing material.

    摘要翻译： 诸如锂离子电池的电池包括与第一电极相关联的第一电极，第二电极，熔融盐电解质和电子收集器，所述电子收集器包括导电膜。 电池还包括分离电子收集器和第一电极的保护层，保护层包含含碳材料。 电子收集器可以是诸如铝，铝合金，铜，镍，其它金属（例如合金），导电聚合物等的导电材料。 在一个示例中，保护层是石墨层。 在其他实例中，保护层可以是富勒烯膜，碳纳米管膜或其它含碳材料。

    Highly parallel structure for fast multi cycle binary and decimal adder unit
    47.
    发明申请
    Highly parallel structure for fast multi cycle binary and decimal adder unit 审中-公开
    用于快速多周期二进制和十进制加法器单元的高度并行结构

    公开(公告)号：US20060031279A1

    公开(公告)日：2006-02-09

    申请号：US11175489

    申请日：2005-07-06

    申请人： Wilhelm Haller ,  Wen Li ,  Michael Kelly ,  Holger Wetter

    发明人： Wilhelm Haller ,  Wen Li ,  Michael Kelly ,  Holger Wetter

    IPC分类号： G06F7/50

    CPC分类号： G06F7/494 ,  G06F7/508 ,  G06F7/575 ,  G06F2207/4924

    摘要： An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.

    摘要翻译： 一个加法器电路，用于将两个二进制或两个十进制操作数A和B相加，其中运算由输入操作数A和B直接计算而不加加6或减6运算到进位计算中。 对于所有时序关键功能，可以使用简化的输入数据集，即有效的十进制数据，并且不需要单独的检查逻辑排除不存在的十进制数（10至15）。 这降低了逻辑功能的复杂性。

    Optical sight system for use with weapon simulation system
    48.
    发明申请
    Optical sight system for use with weapon simulation system 审中-公开
    用于武器模拟系统的光学瞄准系统

    公开(公告)号：US20050233284A1

    公开(公告)日：2005-10-20

    申请号：US10974543

    申请日：2004-10-27

    申请人： Pando Traykov ,  Zhilie Li ,  Yang Shen ,  Wen Li ,  Jay Luo

    发明人： Pando Traykov ,  Zhilie Li ,  Yang Shen ,  Wen Li ,  Jay Luo

    IPC分类号： G09B19/00

    CPC分类号： F41G3/2611 ,  F41G3/26

    摘要： An optical sight system is used in conjunction with such a weapon simulation system to immerse a user in the interactive simulation by employing an actual weapon sight with a simulated weapon, such that the view through the weapon sight is a clear view of an image on a primary image display. The system includes a secondary image display electrically connected to an image generator to receive the target corresponding to a magnified version of the scenario displayed on the primary image display. To view the image on the secondary image display with the weapon sight, the optical sight system includes an optical lens to correct the long focal distance of the scope and enable it to focus on the secondary image display. Through the use of a laser on the simulated weapon, the system is able to generate the desired magnified view on the secondary image display. Using a system of interpolation and extrapolation, the optical sight system is able to further create a clear magnified view of the primary image display. The system further provides a method for correcting the angle displayed on the secondary image display to compensate for rotation of the weapon simulator as handled by the user.

    摘要翻译： 光学瞄准系统与这样的武器模拟系统结合使用，以将用户通过使用具有模拟武器的实际武器瞄准器来将用户浸入到交互式模拟中，使得通过武器瞄准镜的视野是清晰的视野 主图像显示。 该系统包括电连接到图像发生器以接收对应于在主图像显示器上显示的场景的放大版本的目标的次要图像显示。 要使用武器瞄准镜观看二次图像显示器上的图像，光学瞄准器系统包括一个光学透镜，用于校正示波器的长焦距并使其能够聚焦在二次图像显示上。 通过在模拟武器上使用激光，系统能够在次要图像显示器上产生期望的放大视图。 使用插值和外推系统，光学瞄准系统能够进一步创建主要图像显示的清晰放大视图。 该系统还提供了一种用于校正显示在次级图像显示器上的角度以补偿由用户处理的武器模拟器的旋转的方法。