公开(公告)号：US09449867B2

公开(公告)日：2016-09-20

申请号：US14306643

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Heng Wu ,  Yi-Hsien Chang ,  Kai-Chih Liang ,  Yi Heng Tsai ,  Wei-Cheng Shen ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Han-Chin Chiu

IPC: B81C3/00 ,  B81B7/00 ,  H01L21/762 ,  H01L23/00 ,  H01L27/092

CPC classification number: H01L21/76232 ,  B81B7/0025 ,  B81B7/0054 ,  B81B7/008 ,  B81C1/00238 ,  B81C1/00801 ,  B81C3/001 ,  H01L24/89 ,  H01L27/092

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。

公开(公告)号：US20150364363A1

公开(公告)日：2015-12-17

申请号：US14306643

申请日：2014-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Heng Wu ,  Yi-Hsien Chang ,  Kai-Chih Liang ,  Yi Heng Tsai ,  Wei-Cheng Shen ,  Chun-Ren Cheng ,  Chun-Wen Cheng ,  Han-Chin Chiu

IPC: H01L21/762 ,  B81C3/00 ,  B81B7/00 ,  H01L27/092 ,  H01L23/00

CPC classification number: H01L21/76232 ,  B81B7/0025 ,  B81B7/0054 ,  B81B7/008 ,  B81C1/00238 ,  B81C1/00801 ,  B81C3/001 ,  H01L24/89 ,  H01L27/092

Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.

Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。