公开(公告)号：US20230054577A1

公开(公告)日：2023-02-23

申请号：US17407875

申请日：2021-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Gu-Huan LI

IPC: G11C11/16

Abstract: A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.

公开(公告)号：US20220384462A1

公开(公告)日：2022-12-01

申请号：US17818954

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Geng-Cing LIN ,  Ze-Sian LU ,  Meng-Sheng CHANG ,  Chia-En HUANG ,  Jung-Ping YANG ,  Yen-Huei CHEN

IPC: H01L27/112 ,  H01L21/265 ,  H01L23/528

Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

公开(公告)号：US20220359027A1

公开(公告)日：2022-11-10

申请号：US17815141

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: G11C17/18 ,  G11C17/16 ,  H01L27/112

Abstract: An integrated circuit (IC) device includes a first active region extending along a first direction, a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, and a first metal layer. The first pair of gate regions and the first active region configure a first program transistor and a first read transistor sharing a common source/drain region. The first metal layer includes a first program word line pattern over and coupled to the gate region of the first program transistor, a first read word line pattern over and coupled to the gate region of the first read transistor, a first source line pattern coupled to another source/drain region of the first program transistor, and a first bit line pattern coupled to another source/drain region of the first read transistor.

公开(公告)号：US20220122914A1

公开(公告)日：2022-04-21

申请号：US17229345

申请日：2021-04-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Ting WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Chung-I HUANG

IPC: H01L23/525 ,  H01L27/112

Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.

公开(公告)号：US20220093196A1

公开(公告)日：2022-03-24

申请号：US17541245

申请日：2021-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H01L27/02 ,  H01L27/112 ,  G06F30/392

Abstract: An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.

公开(公告)号：US20220028470A1

公开(公告)日：2022-01-27

申请号：US17143702

申请日：2021-01-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: G11C17/18 ,  H01L27/112 ,  G11C17/16

Abstract: A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor.

公开(公告)号：US20210384203A1

公开(公告)日：2021-12-09

申请号：US17103073

申请日：2020-11-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Chia-En HUANG ,  Yao-Jen YANG ,  Yih WANG

IPC: H01L27/112 ,  H01L23/528 ,  G06F30/392

Abstract: A memory device includes a programming gate-strip, a read gate-strip, and an array of one-bit memory cells. Each one-bit memory cell includes an anti-fuse structure, a transistor, a terminal conductor, a group of programming conducting lines, and a bit connector. The anti-fuse structure has a dielectric layer overlying a semiconductor region in an active zone at an intersection of the programming gate-strip and the active zone. The transistor has a channel region in the active zone at an intersection of the read gate-strip and the active zone. The terminal conductor overlies a terminal region of the transistor in the active zone. The group of programming conducting lines is conductively connected to the programming gate-strip through a group of one or more gate via-connectors. The bit connector is conductively connected to the terminal conductor through one or more terminal via-connectors.

公开(公告)号：US20210280588A1

公开(公告)日：2021-09-09

申请号：US17317162

申请日：2021-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Min-Shin WU ,  Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Yao-Jen YANG

IPC: H01L27/112 ,  G11C17/18 ,  G11C17/16

Abstract: A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

公开(公告)号：US20210173995A1

公开(公告)日：2021-06-10

申请号：US17178973

申请日：2021-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Shao-Yu CHOU ,  Yao-Jen YANG ,  Chen-Ming HUNG

IPC: G06F30/392 ,  H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L23/528

Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and a first active area, and a second anti-fuse structure including a second dielectric layer between a second gate conductor and the first active area. A first via is electrically connected to the first gate conductor at a first location a first distance from the first active area, a second via is electrically connected to the second gate conductor at a second location a second distance from the first active area, and the first distance is approximately equal to the second distance.

公开(公告)号：US20210110879A1

公开(公告)日：2021-04-15

申请号：US17111055

申请日：2020-12-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng CHANG ,  Yao-Jen YANG

IPC: G11C17/16 ,  G06F30/392 ,  G11C17/18 ,  H01L27/02 ,  H01L27/112 ,  H01L23/525

Abstract: An IC structure includes a first FinFET including a first plurality of gate structures overlying a first plurality of fin structures, a second FinFET including a second plurality of gate structures overlying a second plurality of fin structures, and an eFuse including a conductive element positioned between the first and second pluralities of gate structures. The conductive element of the eFuse includes a first contact region electrically connected to each of the first and second pluralities of fin structures.