公开(公告)号：US20210020505A1

公开(公告)日：2021-01-21

申请号：US16797990

申请日：2020-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaegwon Jang ,  Seokhyun Lee ,  Jongyoun Kim ,  Minjun Bae

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56

Abstract: A method of manufacturing a semiconductor package is provided including forming a lower redistribution layer. A conductive post is formed on the lower redistribution layer. A semiconductor chip is mounted on the lower redistribution layer. A molding member is formed on the lower redistribution layer. An upper surface of the molding member is at a level lower than an upper surface of the conductive post. An insulating layer is formed on the molding member. An upper surface of the insulating layer is at a level higher than the upper surface of the conductive post. The insulating layer is etched to expose the upper surface of the conductive post. An upper redistribution layer is formed on the insulating layer. The upper redistribution layer is electrically connected to the conductive post.

公开(公告)号：US10741518B2

公开(公告)日：2020-08-11

申请号：US16698117

申请日：2019-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youn Ji Min ,  Seokhyun Lee ,  Jongyoun Kim ,  Kyoung Lim Suk ,  SeokWon Lee

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/10 ,  H01L21/683 ,  H01L23/498

Abstract: A semiconductor package includes: a redistribution substrate; a semiconductor chip on the redistribution substrate; and an external terminal on a bottom surface of the redistribution substrate, wherein the redistribution substrate comprises: a first insulating layer including a first opening; a second insulating layer on the first insulating layer and including a second opening, wherein the second opening is positioned in the first opening in a plan view; a first barrier metal layer disposed along a sidewall of the first opening and along a sidewall of the second opening; a first redistribution conductive pattern on the first barrier metal layer; a third insulating layer on a bottom surface of the first insulating layer; and a pad penetrating the third insulating layer and electrically connecting to the first redistribution conductive pattern, wherein the external terminal is provided on the pad, wherein the second insulating layer at least partially covers a chip pad of the semiconductor chip, and the second opening at least partially exposes the chip pad, wherein, inside the second insulating layer, the first barrier metal layer is in contact with the chip pad through the second opening, and wherein the first redistribution conductive pattern has a surface roughness including protrusions extending in a range of from about 0.01 μm to about 0.5 μm, and the first insulating layer has a surface roughness smaller than the surface roughness of the first redistribution conductive pattern.

公开(公告)号：US20190181064A1

公开(公告)日：2019-06-13

申请号：US16279118

申请日：2019-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongyoun Kim ,  Seokhyun Lee

IPC: H01L21/66 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.