公开(公告)号：US20220173942A1

公开(公告)日：2022-06-02

申请号：US17393811

申请日：2021-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sucheol Lee ,  Changkyu Seol ,  Byungsuk Woo

IPC: H04L25/03

Abstract: A receiver included in a memory device includes a flag generator circuit, an equalizer circuit and an equalization controller circuit. The flag generator circuit is configured to, during a normal operation mode, generates a flag signal without an external command. The equalizer circuit is configured to, during the normal operation mode, receive an input data signal through a channel, generate an equalized signal by equalizing the input data signal based on an equalization coefficient, and generate a data sample signal including a plurality of data bits based on the equalized signal. The equalization controller circuit is configured to, during the normal operation mode, determine an amount of change in the equalization coefficient based on the flag signal, the equalized signal and the data sample signal, and perform a training operation in which the equalization coefficient is updated in real time based on the amount of change in the equalization coefficient.

公开(公告)号：US09336887B2

公开(公告)日：2016-05-10

申请号：US14512965

申请日：2014-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Euncheol Kim ,  Junjin Kong ,  Hong Rak Son

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5641 ,  H01L27/11578

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract translation: 非易失性存储器件包括具有多个存储块的存储单元阵列。 每个存储块包括布置在多个字线和多个位线的交点处的存储器单元。 多个字线的至少一个字线被包括在上部字线组中，并且多个字线的至少一个其它字线被包括在下部字线组中。 连接到包括在上部字线组中的至少一个字线的存储器单元中存储的数据位的数量不同于存储在连接到包含在下一个字中的至少一个其它字线的存储器单元中的数据位的数量 线组。