公开(公告)号：US08812789B2

公开(公告)日：2014-08-19

申请号：US13894545

申请日：2013-05-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Erich James Plondke ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令，编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。

公开(公告)号：US20140208027A1

公开(公告)日：2014-07-24

申请号：US14219034

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Christopher Edward Koob ,  Ajay Anant Ingle ,  Lucian Codrescu ,  Jian Shen

IPC: G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0864 ,  G06F17/505 ,  G06F2212/2515 ,  G06F2212/601

Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.

Abstract translation: 一种方法包括在高速缓存的标签状态阵列处接收地址，其中高速缓存可配置为具有小于第一大小的第一大小和第二大小。 所述方法还包括将所述地址的第一部分识别为设置索引，其中当所述高速缓冲存储器具有所述第一大小时，所述第一部分具有相同的位数，就像所述高速缓存具有所述第二大小一样。 所述方法还包括使用所述设置索引来定位所述标签状态阵列的至少一个标签字段，识别所述地址的第二部分以与存储在所述至少一个标签字段处的值进行比较，以定位所述标签状态阵列的至少一个状态字段 标签状态阵列，其与与第二部分匹配的特定标签字段相关联，基于当高速缓存具有该地址时，该地址的第三部分与至少一个状态字段的至少一个状态位的比较来识别高速缓存行 第二大小，并检索高速缓存行。

公开(公告)号：US20140181468A1

公开(公告)日：2014-06-26

申请号：US14189313

申请日：2014-02-25

Applicant: QUALCOMM Incorporated

Inventor： Muhammad Ahmed ,  Erich James Plondke ,  Lucian Codrescu ,  William C. Anderson

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/3012 ,  G06F9/3851 ,  G06F9/3885

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.

Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。 处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。 多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。 此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

公开(公告)号：US20130254489A1

公开(公告)日：2013-09-26

申请号：US13894545

申请日：2013-05-15

Applicant: QUALCOMM Incorporated

Inventor： Ajay Anant Ingle ,  Erich James Plondke ,  Lucian Codrescu

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/121 ,  G06F2212/1016 ,  Y02D10/13

Abstract: A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement.

Abstract translation: 计算机可读存储介质包括当由处理器执行时使处理器通过索引指令，编码方式值和递增器输出值来接收包括在高速缓存无效中的索引值的指令。 指令进一步导致处理器响应于通过索引指令接收到高速缓存无效而将索引值分配为标识符值。 标识符值表示用于替换的高速缓存行。