Abstract:
A pixel cell includes a photodiode disposed in an epitaxial layer in a first region of semiconductor material to accumulate image charge. A floating diffusion is disposed in a well region disposed in the epitaxial layer in the first region. A transfer transistor is coupled to selectively transfer the image charge from the photodiode to the floating diffusion. A deep trench isolation (DTI) structure disposed in the semiconductor material. The DTI structure isolates the first region of the semiconductor material on one side of the DTI structure from a second region of the semiconductor material on an other side of the DTI structure. The DTI structure includes a doped semiconductor material disposed inside the DTI structure that is selectively coupled to a readout pulse voltage in response to the transfer transistor selectively transferring the image charge from the photodiode to the floating diffusion.
Abstract:
An image sensor pixel includes a first photodiode and a second photodiode disposed in a semiconductor material. The first photodiode has a first doped region, a first lightly doped region, and a first highly doped region. The second photodiode has a second full well capacity substantially equal to a first full well capacity of the first photodiode, and includes a second doped region, a second lightly doped region, and a second highly doped region. The image sensor pixel also includes a first microlens optically coupled to direct a first amount of image light to the first photodiode, and a second microlens optically coupled to direct a second amount of image light to the second photodiode. The first amount of image light is larger than the second amount of image light.
Abstract:
A pixel cell includes a photodiode disposed within a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. A transfer transistor is disposed within the first semiconductor chip and coupled to the photodiode to transfer the image charge from the photodiode. A bias voltage generation circuit disposed within a second semiconductor chip for generating a bias voltage. The bias voltage generation circuit is coupled to the first semiconductor chip to bias the photodiode with the bias voltage. The bias voltage is negative with respect to a ground voltage of the second semiconductor chip. A floating diffusion is disposed within the second semiconductor chip. The transfer transistor is coupled to transfer the image charge from the photodiode on the first semiconductor chip to the floating diffusion on the second semiconductor chip.
Abstract:
Techniques and mechanisms to improve potential well characteristics in a pixel cell. In an embodiment, a coupling portion of a pixel cell couples a reset transistor of the pixel cell to a floating diffusion node of the pixel cell, the reset transistor to reset a voltage of the floating diffusion node. In another embodiment, the pixel cell includes a shield line which extends athwart the coupling portion, where the shield line is to reduce a parasitic capacitance of the reset transistor to the floating diffusion node.
Abstract:
A CMOS photodiode device for use in a dual-sensitivity imaging pixel contains at least two areas of differential doping. Transistors are provided in electrical contact with these areas to govern operation of signals emanating from the photodiode on two channels, each associated with a different sensitivity to light. A plurality of such photodiodes may be incorporate into a shared arrangement forming a single pixel, in order to enhance the signals.
Abstract:
A pixel circuit includes a photodiode in semiconductor material to accumulate image charge in response to incident light. A tri-gate charge transfer block coupled includes a single shared channel region the semiconductor material. A transfer gate, shutter gate, and switch gate are disposed proximate to the single shared channel region. The transfer gate transfers image charge accumulated in the photodiode to the single shared channel region in response to a transfer signal. The shutter gate transfers the image charge in the single shared channel region to a floating diffusion in the semiconductor material in response to a shutter signal. The switch gate is configured to couple the single shared channel region to a charge storage structure in the semiconductor material in response to a switch signal.
Abstract:
An image sensor includes a photodiode disposed in a semiconductor material to generate image charge in response to incident light, and a first transfer gate is coupled to the photodiode to extract image charge from the photodiode in response to a first transfer signal. A first storage gate is coupled to the first transfer gate to receive the image charge from the first transfer gate, and a first output gate is coupled to the first storage gate to receive the image charge from the first storage gate. A first capacitor is coupled to the first output gate to store the image charge.
Abstract:
An image sensor has an array of pixel blocks, and each pixel block having associated shutter transistors with each coupled to transfer an image signal comprising a charge dependent on light exposure of a selected pixel onto an image storage capacitor of a plurality of image storage capacitors associated with the pixel block, the image storage capacitors of the pixel block configured to be read through a differential amplifier into an analog to digital converter. The differential amplifier of each pixel block receives a second input from a single reset-sampling capacitor associated with the pixel block. The single reset-sampling capacitor is loaded when the pixels of the pixel block are reset.
Abstract:
An image sensor has an array of pixels, each pixel having an associated shutter transistor coupled to transfer a charge dependent on light exposure of the pixel onto an image storage capacitor, the image-storage capacitors being configured to be read into an analog to digital converter. The shutter transistors are P-type transistors in N-wells, the wells held at an analog power voltage to reduce sensitivity of pixels to dark current; in an alternative embodiment the shutter transistors are N-type transistors in P-wells, the wells held at an analog ground voltage.
Abstract:
A pixel array for use in a high dynamic range image sensor includes a plurality of pixels arranged in a plurality of rows and columns in the pixel array. Each one of the pixels includes a linear subpixel and a log subpixel disposed in a semiconductor material. The linear subpixel is coupled to generate a linear output signal having a linear response, and the log subpixel is coupled to generate a log output signal having a logarithmic response in response to the incident light. A bitline is coupled to the linear subpixel and to the log subpixel to receive the linear output signal and the log output signal. The bitline is one of a plurality of bitlines coupled to the plurality of pixels. Each one of the plurality of bitlines is coupled to a corresponding grouping of the plurality of pixels.