公开(公告)号：US20150155002A1

公开(公告)日：2015-06-04

申请号：US14616753

申请日：2015-02-09

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: G11B20/10 ,  H04N9/87

CPC classification number: G11B20/10527 ,  G09G5/001 ,  G11B2020/10675 ,  H04N9/87 ,  H04N19/129 ,  H04N19/13 ,  H04N19/174 ,  H04N19/423 ,  H04N19/44 ,  H04N21/44004

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

Abstract translation: 一种用于缓冲装置的读指针维护方法，其被设置为缓冲其中包括多个瓦片的多瓦片编码图像的数据，包括以下步骤：判断多瓦片编码的第一瓦片的解码 图片遇到第一瓦片的瓦片边界; 并且当判断遇到第一瓦片的瓦片边界时，将当前使用的读取指针存储到指针缓冲器中，并且从指针缓冲器加载所选择的读取指针以充当当前使用的读取指针。

公开(公告)号：US20130076770A1

公开(公告)日：2013-03-28

申请号：US13681426

申请日：2012-11-20

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: G09G5/00

CPC classification number: G11B20/10527 ,  G09G5/001 ,  G11B2020/10675 ,  H04N9/87 ,  H04N19/129 ,  H04N19/13 ,  H04N19/174 ,  H04N19/423 ,  H04N19/44 ,  H04N21/44004

Abstract: A method for read pointer maintenance of a buffering apparatus, which is arranged to buffer data of a multi-tile encoded picture having a plurality of tiles included therein, includes the following steps: judging if decoding of a first tile of the multi-tile encoded picture encounters a tile boundary of the first tile; and when it is judged that the tile boundary of the first tile is encountered, storing a currently used read pointer into a pointer buffer, and loading a selected read pointer from the pointer buffer to act as the currently used read pointer.

公开(公告)号：US20250063207A1

公开(公告)日：2025-02-20

申请号：US18793979

申请日：2024-08-05

Applicant: MEDIATEK INC.

Inventor： Tung-Hsing Wu ,  Han-Liang Chou ,  Chia-Yun Cheng

IPC: H04N19/85 ,  H04N19/13 ,  H04N19/132 ,  H04N19/172 ,  H04N19/176 ,  H04N19/186 ,  H04N19/70

Abstract: A video processing apparatus includes a video encoding circuit and a post-processing circuit. The video encoding circuit receives a first source data, and encodes the first source data to generate a first bitstream, wherein the first source data includes a first source luminance channel data and a first source chrominance channel data, and the first bitstream includes a first compressed luminance channel data and a first compressed chrominance channel data. The post-processing circuit derives an auxiliary compressed chrominance channel data from an auxiliary input, and generates and outputs an output bitstream that includes the first compressed luminance channel data and the auxiliary compressed chrominance channel data.

公开(公告)号：US20230122258A1

公开(公告)日：2023-04-20

申请号：US17871976

申请日：2022-07-24

Applicant: MEDIATEK INC.

Inventor： Ming-Hsien Lai ,  Min-Hao Chiu ,  Chia-Yun Cheng

IPC: H04N19/89 ,  H04N19/60 ,  H04N19/176 ,  H04N19/70

Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.

公开(公告)号：US20230100895A1

公开(公告)日：2023-03-30

申请号：US17945115

申请日：2022-09-15

Applicant: MEDIATEK INC.

Inventor： Li-Ren Huang ,  Chia-Yun Cheng ,  Min-Hao Chiu ,  Hsueh-Yen Shen

IPC: H04N19/423 ,  G06F12/08

Abstract: A video processing circuit includes a first buffer and a computation circuit. Before a second one-dimensional processing operation is performed upon a plurality of consecutive blocks in a second direction, the first computation circuit generates a first processing result for each of the plurality of consecutive blocks by performing a first one-dimensional processing operation upon each of the plurality of consecutive blocks in a first direction that is different from the second direction, and further stores a plurality of first processing results of the plurality of consecutive blocks into the first buffer.

公开(公告)号：US20230059794A1

公开(公告)日：2023-02-23

申请号：US17855829

申请日：2022-07-01

Applicant: MEDIATEK INC.

Inventor： Sheng-Jen Wang ,  Chao-I Wu ,  Ming-Long Wu ,  Chia-Yun Cheng

IPC: H04N19/44 ,  H04N19/13 ,  H04N19/423

Abstract: A context-based adaptive binary arithmetic coding (CABAC) decoder includes a bin decode circuit and a context update circuit. The bin decode circuit supports decoding of multiple bins in one cycle. The multiple bins include a first bin and a second bin. The bin decode circuit generates a bin value of the first bin according to a first set of multiple contexts, a first range and a first offset, and generates one bin value of the second bin according to a second set of multiple contexts, a second range and a second offset. The context update circuit updates the first set of multiple contexts in response to the bin value of the first bin, to generate a first set of multiple updated contexts, and updates the second set of multiple contexts in response to said one bin value of the second bin, to generate a second set of multiple updated contexts.

公开(公告)号：US20190281312A1

公开(公告)日：2019-09-12

申请号：US16293647

申请日：2019-03-06

Applicant: MEDIATEK INC.

Inventor： Chi-Min Chen ,  Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/186 ,  H04N19/182 ,  H04N19/119 ,  H04N19/157 ,  H04N19/44 ,  H04N19/91

Abstract: A palette decoding apparatus includes a palette color storage device which stores palette colors, a color index storage device which stores color indices of pixels, and a palette value processing circuit which generates a palette value for each pixel by reading data from the color index storage device and the palette color storage device. A frame is divided into first coding units, and each first coding unit is sub-divided into one or more second coding units. Before a palette value of a last pixel in a first coding unit is generated by the palette value processing circuit, a palette value of a non-last pixel in the first coding unit is generated by the palette value processing circuit and used by a reconstruction circuit of the video decoder.

公开(公告)号：US10250912B2

公开(公告)日：2019-04-02

申请号：US15016221

申请日：2016-02-04

Applicant: MEDIATEK INC.

Inventor： Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/91

Abstract: An apparatus is capable of achieving high-throughput entropy decoding, and includes an arithmetic decoding processing circuitry and a variable-length decoder (VLD). The arithmetic decoding processing circuitry receives a video bitstream through a bitstream input, applies arithmetic decoding to at least a portion of the video bitstream to derive one or more arithmetic-decoded binary strings containing no arithmetic encoded binary string, and stores the arithmetic-decoded binary strings in the storage device. The variable-length decoder is coupled to the arithmetic decoding processing circuitry, the storage device and a VLD output. The variable-length decoder receives at least a portion of arithmetic-decoded bitstream when arithmetic-decoded bitstreams stored in the storage device are complete for a selected image unit, decodes at least a portion of arithmetic-decoded bitstream into one or more decoded syntax elements, and provides the decoded syntax elements through the VLD output.

公开(公告)号：US20180020228A1

公开(公告)日：2018-01-18

申请号：US15644815

申请日：2017-07-09

Applicant: MEDIATEK INC.

Inventor： Ming-Long Wu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/91 ,  H04N19/70

CPC classification number: H04N19/44 ,  H04N19/436 ,  H04N19/70 ,  H04N19/91

Abstract: A video processing system includes a storage device, a demultiplexing circuit, and a syntax parser. The storage device includes a first buffer and a second buffer. The demultiplexing circuit performs a demultiplexing operation upon an input bitstream to write a video bitstream into the first buffer and write start points of bitstream segments of the video bitstream stored in the first buffer into the second buffer. Each start point is indicative of a start address of a corresponding bitstream segment stored in the first buffer. The syntax parser includes syntax parsing circuits and a syntax parsing control circuit. The syntax parsing control circuit fetches a start point from the second buffer, assigns the fetched start point to a syntax parsing circuit, and triggers the selected syntax parsing circuit to start syntax parsing of a bitstream segment that is read from the first buffer according to the fetched start point.

公开(公告)号：US20170251218A1

公开(公告)日：2017-08-31

申请号：US15438774

申请日：2017-02-22

Applicant: MEDIATEK INC.

Inventor： Min-Hao Chiu ,  Chia-Yun Cheng ,  Yung-Chang Chang

IPC: H04N19/44 ,  H04N19/129 ,  H04N19/436 ,  H04N19/124 ,  H04N19/60

CPC classification number: H04N19/436 ,  H04N19/61

Abstract: A residual processing circuit has a single-path pipeline and a single-path controller. The single-path pipeline has an inverse scan (IS) circuit, an inverse quantization (IQ) circuit and an inverse transform (IT) circuit arranged to process a current non-zero residual data block in a pipeline manner. The current non-zero residual data block is at least a portion of a transform unit. The single-path controller controls pipelined processing of the current non-zero residual data block at the single-path pipeline. The single-path controller instructs the IS circuit to start IS processing of a next non-zero residual data block before the IT circuit finishes a first half of IT processing of the current non-zero residual data block.