-
公开(公告)号：US20180063158A1
公开(公告)日：2018-03-01
申请号：US15252392
申请日：2016-08-31
CPC分类号： H04L9/083 , G06F21/575 , H04L9/0891 , H04L9/0894 , H04L9/3242
摘要： Example implementations relate to cryptographic evidence of persisted capabilities. In an example implementation, in response to a request to access a persisted capability stored in a globally shared memory, a system may decide whether to trust the persisted capability by verification of cryptographic evidence accompanying the persisted capability. The system may load the persisted capability upon a decision to trust the persisted capability based on successful verification.
-
公开(公告)号：US20180032373A1
公开(公告)日：2018-02-01
申请号：US15223394
申请日：2016-07-29
发明人： Yuan Chen , Dejan S. Milojicic , Dazhao Cheng
CPC分类号： G06F9/5027 , G06F9/5038 , G06F2209/5011 , G06N99/005
摘要： Examples relate to managing data processing resources. In one example, a computing device may: determine, for each of a plurality of data processing jobs, that the job is independent or dependent; allocate data processing resources to an independent job processing pool or a dependent job processing pool based on an initial resource share value indicating how resources are to be allocated between job processing pools; determine a first policy for scheduling data to be processed by processing resources allocated to the independent job processing pool; determine a second policy for scheduling data to be processed by processing resources allocated to the dependent job processing pool; determine an initial parallelism value that specifies a number of concurrently processing jobs; and provide a processing device with instructions to process batches of data using the allocation of data processing resources, the first policy, the second policy, and the initial parallelism value.
-
公开(公告)号：US09575542B2
公开(公告)日：2017-02-21
申请号：US13755527
申请日：2013-01-31
CPC分类号： G06F1/324 , G06F1/3206 , G06F1/3275 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/14 , Y02D10/172 , Y02D10/22
摘要： A power management module can select one of a plurality of different operational modes for a hardware component in a computer system based on application performance and total computer system power consumption determined for each of the operational modes.
摘要翻译： 功率管理模块可以基于针对每个操作模式确定的应用性能和总计算机系统功耗，来选择计算机系统中的硬件组件的多种不同操作模式之一。
-
公开(公告)号：US20240112029A1
公开(公告)日：2024-04-04
申请号：US18528935
申请日：2023-12-05
发明人： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , John Paul Strachan , Sergey Serebryakov
CPC分类号： G06N3/08 , G11C13/0069 , G11C2213/77
摘要： A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
-
公开(公告)号：US20240111970A1
公开(公告)日：2024-04-04
申请号：US18528086
申请日：2023-12-04
发明人： John Paul Strachan , Dejan S. Milojicic , Martin Foltin , Sai Rahul Chalamalasetti , Amit S. Sharma
摘要： In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.
-
公开(公告)号：US11119941B2
公开(公告)日：2021-09-14
申请号：US15799153
申请日：2017-10-31
IPC分类号： G06F12/14 , G06F12/1027 , G06F12/1009
摘要： According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.
-
公开(公告)号：US20210201136A1
公开(公告)日：2021-07-01
申请号：US17044633
申请日：2018-04-30
发明人： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , John Paul Strachan , Sergey Serebryakov
摘要： A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.
-
公开(公告)号：US10795782B2
公开(公告)日：2020-10-06
申请号：US15942925
申请日：2018-04-02
摘要： Example implementations relate to an apparatus to support providing a computing service to a client including transferring control between a primary data processing system and a secondary data processing system in response to an event; the primary data processing system comprising a processor and associated memory and the secondary data processing system comprising a processor and associated memory; the apparatus comprising: circuitry to identify restoration data; the restoration data comprising at least data associated with at least one predetermined type of memory operation of the memory associated with the primary data processing system, and circuitry to output any identified restoration data for storage in the memory associated with the processor of the secondary data processing system.
-
49.发明申请公开(公告)号：US20200073755A1
公开(公告)日：2020-03-05
申请号：US16115100
申请日：2018-08-28
发明人： John Paul Strachan , Catherine Graves , Dejan S. Milojicic , Paolo Faraboschi , Martin Foltin , Sergey Serebryakov
摘要： A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
-
公开(公告)号：US20200042287A1
公开(公告)日：2020-02-06
申请号：US16052218
申请日：2018-08-01
发明人： Sai Rahul Chalamalasetti , Paolo Faraboschi , Martin Foltin , Catherine Graves , Dejan S. Milojicic , Sergey Serebryakov , John Paul Strachan
摘要： Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.
-
-
-
-
-
-
-
-
-
搜索结果
75 条记录 (耗时 0.024 秒)
